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參數(shù)資料
| 型號(hào)： | ISL23325WFRUZ-TK |
| 廠商： | Intersil |
| 文件頁數(shù)： | 6/20頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DGTL POT 256POS 10K 16UTQFN |
| 標(biāo)準(zhǔn)包裝： | 1,000 |
| 系列： | XDCP™ |
| 接片： | 256 |
| 電阻（歐姆）： | 10k |
| 電路數(shù)： | 2 |
| 溫度系數(shù)： | 標(biāo)準(zhǔn)值 125 ppm/°C |
| 存儲(chǔ)器類型： | 易失 |
| 接口： | I²C，2 線串口 |
| 電源電壓： | 1.2 V ~ 5.5 V，1.7 V ~ 5.5 V |
| 工作溫度： | -40°C ~ 125°C |
| 安裝類型： | * |
| 封裝/外殼： | * |
| 供應(yīng)商設(shè)備封裝： | * |
| 包裝： | * |
ISL23325
14
FN7870.0
June 21, 2011
SERIAL CLOCK (SCL)
This input is the serial clock of the I2C serial interface. SCL
requires an external pull-up resistor, since a master is an open
drain output.
DEVICE ADDRESS (A2, A1, A0)
The address inputs are used to set the least significant 3 bits of
the 7-bit I2C interface slave address. A match in the slave
address serial data stream must match with the Address input
pins in order to initiate communication with the ISL23325. A
maximum of eight ISL23325 devices may occupy the I2C serial
bus (see Table 3).
VLOGIC
Digital power source for the logic control section. It supplies an
internal level translator for 1.2V to 5.5V serial bus operation. Use
the same supply as the I2C logic source.
Principles of Operation
The ISL23325 is an integrated circuit incorporating two DCPs with
its associated registers and an I2C serial interface providing direct
communication between a host and the potentiometer. The resistor
array is comprised of individual resistors connected in series. At
either end of the array and between each resistor is an electronic
switch that transfers the potential at that point to the wiper.
The electronic switches on the device operate in a
“make-before-break” mode when the wiper changes tap positions.
Voltage at any DCP pins, RHi, RLi or RWi, should not exceed VCC
level at any conditions during power-up and normal operation.
The VLOGIC pin is the terminal for the logic control digital power
source. It should use the same supply as the I2C logic source
which allows reliable communication with a wide range of
microcontrollers and is independent from the VCC level. This is
extremely important in systems where the master supply has
lower levels than DCP analog supply.
DCP Description
Each DCP is implemented with a combination of resistor elements
and CMOS switches. The physical ends of each DCP are equivalent
to the fixed terminals of a mechanical potentiometer (RHi and RLi
pins). The RWi pin of the DCP is connected to intermediate nodes,
and is equivalent to the wiper terminal of a mechanical
potentiometer. The position of the wiper terminal within the DCP is
controlled by an 8-bit volatile Wiper Register (WRi). When the WRi
of a DCP contains all zeroes (WRi[7:0] = 00h), its wiper terminal
(RWi) is closest to its “Low” terminal (RLi). When the WRi register
of a DCP contains all ones (WRi[7:0] = FFh), its wiper terminal
(RWi) is closest to its “High” terminal (RHi). As the value of the WRi
increases from all zeroes (0) to all ones (255 decimal), the wiper
moves monotonically from the position closest to RLi to the
position closest to RHi. At the same time, the resistance between
RWi and RLi increases monotonically, while the resistance
between RHi and RWi decreases monotonically.
While the ISL23325 is being powered up, both WR0 and WR1
are reset to 80h (128 decimal), which positions RWi at the center
between RLi and RHi.
The WRi can be read or written to directly using the I2C serial
interface as described in the following sections.
Memory Description
The ISL23325 contains three volatile 8-bit registers: Wiper
Register WR0, Wiper Register WR1, and Access Control Register
(ACR). Memory map of the ISL23325 is shown in Table 1. The
Wiper Register WR0 at address 0, contains current wiper position
of DCP0; The Wiper Register WR1 at address 1 contains current
wiper position of DCP1. The Access Control Register (ACR) at
address 10h contains information and control bits described in
Table 2.
Shutdown Function
The SHDN bit (ACR[6]) disables or enables shutdown mode for all
DCP channels simultaneously. When this bit is 0, i.e., DCP is forced
to end-to-end open circuit and RW is connected to RL through a
2k serial resistor as shown in Figure 25. Default value of the
SHDN bit is 1.
When the device enters shutdown, all current DCP WR settings are
maintained. When the device exits shutdown, the wipers will return
to the previous WR settings after a short settling time (see
Figure 26).
In shutdown mode, if there is a glitch on the power supply which
causes it to drop below 1.3V for more than 0.2 to 0.4s, the
wipers will be RESET to their mid position. This is done to avoid
an undefined state at the wiper outputs.
TABLE 1. MEMORY MAP
ADDRESS
(hex)
VOLATILE
REGISTER NAME
DEFAULT SETTING
(hex)
10
ACR
40
1WR1
80
0WR0
80
TABLE 2. ACCESS CONTROL REGISTER (ACR)
BIT #
7
6
5
4
32
10
NAME/
VALUE
0SHDN
0
00
FIGURE 25. DCP CONNECTION IN SHUTDOWN MODE
2k
RW
RL
RH
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