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參數(shù)資料
| 型號(hào)： | ISL22444WFR20Z-TK |
| 廠(chǎng)商： | Intersil |
| 文件頁(yè)數(shù)： | 5/19頁(yè) |
| 文件大小： | 0K |
| 描述： | IC POT DGTL 256TP LN LP 20-QFN |
| 產(chǎn)品培訓(xùn)模塊： | Solutions for Industrial Control Applications |
| 標(biāo)準(zhǔn)包裝： | 1,000 |
| 系列： | XDCP™ |
| 接片： | 256 |
| 電阻（歐姆）： | 10k |
| 電路數(shù)： | 4 |
| 溫度系數(shù)： | 標(biāo)準(zhǔn)值 ±85 ppm/°C |
| 存儲(chǔ)器類(lèi)型： | 非易失 |
| 接口： | 4 線(xiàn) SPI（芯片選擇） |
| 電源電壓： | 2.25 V ~ 5.5 V |
| 工作溫度： | -40°C ~ 125°C |
| 安裝類(lèi)型： | 表面貼裝 |
| 封裝/外殼： | 20-VQFN 裸露焊盤(pán) |
| 供應(yīng)商設(shè)備封裝： | 20-QFN 裸露焊盤(pán)（5x5） |
| 包裝： | 帶卷 (TR) |
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13
FN6426.0
May 24, 2007
on the falling edge of SCK. CS must be LOW during
communication with the ISL22444. SCK and CS lines are
controlled by the host or master. The ISL22444 operates
only as a slave device.
All communication over the SPI interface is conducted by
sending the MSB of each byte of data first.
Protocol Conventions
The SPI protocol contains Instruction Byte followed by one
or more Data Bytes. A valid Instruction Byte contains
instruction as the three MSBs, with the following five register
address bits (see Table 3).
The next byte sent to the ISL22444 is the Data Byte.
TABLE 3. INSTRUCTION BYTE FORMAT
Table 4 contains a valid instruction set for ISL22444.
There are only sixteen register addresses possible for this
DCP. If the [R4:R0] bits are 00000, 00001, 00010 or 00011
then the read or write is to either the IVRi or the WRi
registers (depends of VOL bit at ACR). If the [R4:R0] are
10000, then the operation is on the ACR.
Write Operation
A Write operation to the ISL22444 is a two or more bytes
operation. First, It requires, the CS transition from HIGH to
LOW. Then host must send a valid Instruction Byte followed
by one or more Data Bytes to SDI pin. The host terminates
the write operation by pulling the CS pin from LOW to HIGH.
Instruction is executed on rising edge of CS. For a write-to
address 00h, 01h, 02h or 03h, the MSB of the byte at
address 10h (ACR[7]) determines if the Data Byte is to be
written to volatile or both volatile and non-volatile registers.
Refer to “Memory Description” and Figure 16. Note: the
internal non-volatile write cycle starts with the rising edge of
CS and requires up to 20ms. During non-volatile write cycle
the read operation to ACR register is allowed to check WIP
bit.
Read Operation
A Read operation to the ISL22444 is a four byte operation. It
requires first, the CS transition from HIGH to LOW. Then the
host must send a valid Instruction Byte followed by “dummy”
Data Byte, a NOP Instruction Byte and another “dummy”
Data Byte to SDI pin. The SPI host receives the Instruction
Byte (instruction code + register address) and requested
Data Byte from SDO pin on rising edge of SCK during third
and fourth bytes respectively. The host terminates the read
operation by pulling the CS pin from LOW to HIGH (see
Figure 17). Reading from the IVRi will not change the WRi, if
its contents are different.
BIT #
76
54
32
1
0
I2
I1
I0
R4
R3
R2
R1
R0
TABLE 4. INSTRUCTION SET
INSTRUCTION SET
OPERATION
I2
I1
I0
R4
R3
R2
R1
R0
0
X
XXX
NOP
0
1
X
XXX
ACR READ
0
1
X
XXX
ACR WRITE
1
0
R4R3R2
R1R0
WR, IVR, GP or ACR READ
1
0
R4R3R2
R1R0
WR, IVR, GP or ACR WRITE
where X means “do not care”.
CS
SCK
SDI
SDO
WR INSTRUCTION
DATA BYTE
1
3
4
5
7
8
9
1011
1213141516
26
ADDR
FIGURE 16. TWO BYTE WRITE SEQUENCE
ISL22444
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| ISL22444WFV20Z | 功能描述:數(shù)字電位計(jì) IC 269 TAP FL RNG IND QD SPI DCP 20LD RoHS:否 制造商:Maxim Integrated 電阻:200 Ohms 溫度系數(shù):35 PPM / C 容差:25 % POT 數(shù)量:Dual 每 POT 分接頭:256 弧刷存儲(chǔ)器:Volatile 緩沖刷: 數(shù)字接口:Serial (3-Wire, SPI) 描述/功能:Dual Volatile Low Voltage Linear Taper Digital Potentiometer 工作電源電壓:1.7 V to 5.5 V 電源電流:27 uA 最大工作溫度:+ 125 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TQFN-16 封裝:Reel |
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| ISL22446 | 制造商:INTERSIL 制造商全稱(chēng):Intersil Corporation 功能描述:Quad Digitally Controlled Potentiometer XDCP |
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