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參數(shù)資料
型號： ISL22323UFR16Z-TK
廠商： Intersil
文件頁數(shù)： 16/18頁
文件大小： 0K
描述： IC POT DGTL 256TP LN LP 16-QFN
產(chǎn)品培訓模塊： Solutions for Industrial Control Applications
標準包裝： 1,000
系列： XDCP™
接片： 256
電阻（歐姆）： 50k
電路數(shù)： 2
溫度系數(shù)： 標準值 ±45 ppm/°C
存儲器類型： 非易失
接口： I²C（設備位址）
電源電壓： 2.25 V ~ 5.5 V
工作溫度： -40°C ~ 125°C
安裝類型： 表面貼裝
封裝/外殼： 16-VFQFN 裸露焊盤
供應商設備封裝： 16-QFN-EP（4x4）
包裝： 帶卷 (TR)
7
FN6422.1
March 13, 2008
EEPROM SPECIFICATION
EEPROM Endurance
1,000,000
Cycles
EEPROM Retention
Temperature T
≤ +55°C
50
Years
tWC
(Note 20)
Non-volatile Write Cycle Time
12
20
ms
SERIAL INTERFACE SPECS
VIL
A0, A1, A2, SDA, and SCL Input
Buffer LOW Voltage
0.3*VCC
V
VIH
A0, A1, A2, SDA, and SCL Input
Buffer HIGH Voltage
0.7*VCC
V
Hysteresis
(Note 19)
SDA and SCL Input Buffer Hysteresis
0.05*VCC
V
VOL
(Note 19)
SDA Output Buffer LOW Voltage,
Sinking 4mA
00.4
V
Cpin
(Note 19)
A0, A1, A2, SDA, and SCL Pin
Capacitance
10
pF
fSCL
SCL Frequency
400
kHz
tsp
Pulse Width Suppression Time at SDA
and SCL Inputs
Any pulse narrower than the max spec is
suppressed
50
ns
tAA
(Note 19)
SCL Falling Edge to SDA Output Data
Valid
SCL falling edge crossing 30% of VCC, until
SDA exits the 30% to 70% of VCC window
900
ns
tBUF
(Note 19)
Time the Bus Must be Free Before The
Start of a New Transmission
SDA crossing 70% of VCC during a STOP
condition, to SDA crossing 70% of VCC
during the following START condition
1300
ns
tLOW
Clock LOW Time
Measured at the 30% of VCC crossing
1300
ns
tHIGH
Clock HIGH Time
Measured at the 70% of VCC crossing
600
ns
tSU:STA
START Condition Setup Time
SCL rising edge to SDA falling edge; both
crossing 70% of VCC
600
ns
tHD:STA
START Condition Hold Time
From SDA falling edge crossing 30% of VCC
to SCL falling edge crossing 70% of VCC
600
ns
tSU:DAT
Input Data Setup Time
From SDA exiting the 30% to 70% of VCC
window, to SCL rising edge crossing 30% of
VCC
100
ns
tHD:DAT
Input Data Hold Time
From SCL rising edge crossing 70% of VCC
to SDA entering the 30% to 70% of VCC
window
0ns
tSU:STO
STOP Condition Setup Time
From SCL rising edge crossing 70% of VCC,
to SDA rising edge crossing 30% of VCC
600
ns
tHD:STO
STOP Condition Hold Time for Read,
or Volatile Only Write
From SDA rising edge to SCL falling edge;
both crossing 70% of VCC
1300
ns
tDH
(Note 19)
Output Data Hold Time
From SCL falling edge crossing 30% of VCC,
until SDA enters the 30% to 70% of VCC
window
0ns
tR
(Note 19)
SDA and SCL Rise Time
From 30% to 70% of VCC
20 +
0.1*Cb
250
ns
tF
(Note 19)
SDA and SCL Fall Time
From 70% to 30% of VCC
20 +
0.1*Cb
250
ns
Operating Specifications Over the recommended operating conditions unless otherwise specified. (Continued)
SYMBOL
PARAMETER
TEST CONDITIONS
MIN
(Note 21)
TYP
(Note 5)
MAX
(Note 21)
UNIT
ISL22323
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