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參數(shù)資料
| 型號： | ISL22323TFV14Z-TK |
| 廠商： | Intersil |
| 文件頁數(shù)： | 5/18頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC POT DGTL 256TP LN LP 14-TSSOP |
| 產(chǎn)品培訓模塊： | Solutions for Industrial Control Applications |
| 標準包裝： | 1,000 |
| 系列： | XDCP™ |
| 接片： | 256 |
| 電阻（歐姆）： | 100k |
| 電路數(shù)： | 2 |
| 溫度系數(shù)： | 標準值 ±45 ppm/°C |
| 存儲器類型： | 非易失 |
| 接口： | I²C（設備位址） |
| 電源電壓： | 2.25 V ~ 5.5 V |
| 工作溫度： | -40°C ~ 125°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 14-TSSOP（0.173"，4.40mm 寬） |
| 供應商設備封裝： | 14-TSSOP |
| 包裝： | 帶卷 (TR) |
13
FN6422.1
March 13, 2008
The non-volatile IVRi and volatile WRi registers are
accessible with the same address.
The Access Control Register (ACR) contains information
and control bits described in Table 2.
The VOL bit (ACR[7]) determines whether the access to
wiper registers WRi or initial value registers IVRi.
If VOL bit is 0, the non-volatile IVRi registers are accessible.
If VOL bit is 1, only the volatile WRi are accessible.
Note: value is written to IVRi register also is written to the
corresponding WRi. The default value of this bit is 0.
The SHDN bit (ACR[6]) disables or enables Shut-down mode.
When this bit is 0, DCPs are in Shut-down mode. Default value
of the SHDN bit is 1.
The WIP bit (ACR[5]) is a read-only bit. It indicates that
non-volatile write operation is in progress. It is impossible to
write to the WRi or ACR while WIP bit is 1.
I2C Serial Interface
The ISL22323 supports an I2C bidirectional bus oriented
protocol. The protocol defines any device that sends data
onto the bus as a transmitter and the receiving device as the
receiver. The device controlling the transfer is a master and
the device being controlled is the slave. The master always
initiates data transfers and provides the clock for both
transmit and receive operations. Therefore, the ISL22323
operates as a slave device in all applications.
All communication over the I2C interface is conducted by
sending the MSB of each byte of data first.
Protocol Conventions
Data states on the SDA line must change only during SCL
LOW periods. SDA state changes during SCL HIGH are
reserved for indicating START and STOP conditions (see
Figure 16). On power-up of the ISL22323, the SDA pin is in
the input mode.
All I2C interface operations must begin with a START
condition, which is a HIGH to LOW transition of SDA while
SCL is HIGH. The ISL22323 continuously monitors the SDA
and SCL lines for the START condition and does not
respond to any command until this condition is met (see
Figure 16). A START condition is ignored during the
power-up of the device.
All I2C interface operations must be terminated by a STOP
condition, which is a LOW to HIGH transition of SDA while
SCL is HIGH (see Figure 16). A STOP condition at the end
of a read operation, or at the end of a write operation places
the device in its standby mode.
An ACK (Acknowledge) is a software convention used to
indicate a successful data transfer. The transmitting device,
either master or slave, releases the SDA bus after
transmitting eight bits. During the ninth clock cycle, the
receiver pulls the SDA line LOW to acknowledge the
reception of the eight bits of data (see Figure 17).
The ISL22323 responds with an ACK after recognition of a
START condition followed by a valid Identification Byte, and
once again after successful receipt of an Address Byte. The
ISL22323 also responds with an ACK after receiving a Data
Byte of a write operation. The master must respond with an
ACK after receiving a Data Byte of a read operation
A valid Identification Byte contains 1010 as the four MSBs,
and the following three bits matching the logic values
present at pins A2, A1 and A0. The LSB is the Read/Write
bit. Its value is “1” for a Read operation and “0” for a Write
operation (See Table 3).
TABLE 3. IDENTIFICATION BYTE FORMAT
7
General Purpose
N/A
6
General Purpose
N/A
5
General Purpose
N/A
4
General Purpose
N/A
3
General Purpose
N/A
2
General Purpose
N/A
1IVR1
WR1
0IVR0
WR0
TABLE 2. ACCESS CONTROL REGISTER (ACR)
BIT #
7
6
5
4
3210
NAME
VOL
SHDN
WIP
0
0000
TABLE 1. MEMORY MAP (Continued)
ADDRESS
(hex)
NON-VOLATILE
VOLATILE
RLi
RWi
RHi
FIGURE 15. DCP CONNECTION IN SHUT-DOWN MODE
1010
A2
A1
A0
R/W
(MSB)
(LSB)
LOGIC VALUES AT PINS A2, A1 AND A0, RESPECTIVELY
ISL22323
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