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參數(shù)資料
| 型號： | ISL1539AIRZ-T13 |
| 廠商： | Intersil |
| 文件頁數(shù)： | 10/23頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC VDSL2 LINE DVR AMP 24QFN |
| 標(biāo)準(zhǔn)包裝： | 2,500 |
| 類型： | 驅(qū)動器 |
| 驅(qū)動器/接收器數(shù)： | 4/4 |
| 規(guī)程： | VDSL2 |
| 電源電壓： | ±5 V ~ 15 V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 24-VFQFN 裸露焊盤 |
| 供應(yīng)商設(shè)備封裝： | 24-QFN（5x4） |
| 包裝： | 帶卷 (TR) |
18
FN6916.0
September 23, 2009
external 2.88kΩ resistor will double the current while
leaving the IADJ pin voltage at approximately -0.4V,
which is well within rated minimum. This approach
should be used with great caution as very high internal
power dissipations can easily be produced. However, it
can be a useful approach to extend operation,
particularly when operating on lower total supply
voltages than the rated typical of ±12V.
The current in RO divides in 1/4 levels to form the bias
current for the 4 pairs of differential switches. Each pair
of switches controls the quiescent current for one port.
For instance, C0AB and C1AB control the quiescent
current for the port constructed from amplifiers A and B.
If both control lines are unconnected externally, the
internal 50kΩ pull-up will switch the differential pairs to
divert the 100A tail currents into the supply turning off
the amplifiers. Taking both control pins low will pass both
IBIAS lines on into scaling current sources. With IREF
grounded, this will give the typical 27.2mA total
quiescent current for a port shown in the “Electrical
while leaving C1 low (<0.8V) will reduce the current into
a port to a typical 23mA. Taking C1 high, while leaving C0
low will reduce the current in a port to a typical 13.5mA
supply current. Table 2 summarizes the operation modes
for ISL1539A for each port.
Performance Considerations
Driving Capacitive Loads
All closed loop op amps are susceptible to reduced phase
margin when driving capacitive loads. This shows up as
peaking in the frequency response that can, in extreme
situations, lead to oscillations. The ISL1539A is designed
to operate successfully with small capacitive loads such
as layout parasitics. As the parasitic capacitance
increases, it is best consider a small resistor in series
with the output to isolate the phase margin effects of the
capacitive load on the differential gain of 10 circuit. With
15pF on each output, we see about 5dB peaking. This will
increase quickly at higher Cloads. If this degree of
peaking is unacceptable, a small series resistor can be
used to improve the flatness as shown in Figure 21.
Output DC Error Model
Often, non-inverting bias current (ibn), inverting bias
current (ibi), and input offset voltage (Vio) are quite low
for typical op amps.
Vio, ibn, ibi can be mapped to output offset both
common and differential mode. Consider the circuit in
Figure 47.
The output common mode offset voltage (Vo-cm) is
derived from the input common mode voltage (Vi-cm),
The output differential mode offset voltage (Vo-dm) is
derived from the input differential mode voltage (Vi-dm),
Example:
Referring to the “Electrical Specification” tables on
ibn = 8A, Δibn = 2A
ibi = 75A, Δibi = 35A
Vio = 8mV, ΔVio = 2mV
TABLE 2. POWER MODES OF THE ISL1539A
C1
C0
OPERATION
00
IS Full Power Mode
01
IS Medium Power Mode
10
IS Low Power Mode
11
Power-Down
COAB
C1AB
IADJ
+3.3V
+VCC I
BIAS
+1.4V
IBIAS +VCC
+3.3V
+1V
50k
C1CD
+3.3V
+VCC I
BIAS
+1.4
V
IBIAS +VCC
+3.3V
50k
COCD
500
RO
FIGURE 46. BIAS CONTROL CIRCUIT
Rcm
Rb
Rf
+Vcc
+
-
Vcm
Rb
Rf
+Vcc
+
-
Zg
± Vio
±Vio
± ibn
±ibi
±ibn
Vcm ± Vocm ± Vodm
FIGURE 47. DC ERROR MODEL
Vicm
2
ibn
Rcm
ibn
Rb
Vio
±
×
±
×
±
=
(EQ. 8)
Vocm
Vicm
±
Rf
ibi
×
±
=
(EQ. 9)
Vidm
ibn
Rb
Vio
Δ
±
×
Δ
±
=
(EQ. 10)
Vodm
Vidm
1
2Rf
Rg
----------
+
ibi
Rf
×
Δ
±
×
±
=
(EQ. 11)
ISL1539A
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