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參數(shù)資料
| 型號： | ISL1218IUZ |
| 廠商： | Intersil |
| 文件頁數(shù)： | 16/21頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC RTC LP BATT BACKED SRAM 8MSOP |
| 產(chǎn)品培訓模塊： | Solutions for Industrial Control Applications |
| 標準包裝： | 50 |
| 類型： | 時鐘/日歷 |
| 特點： | 警報器，閏年，SRAM |
| 存儲容量： | 8B |
| 時間格式： | HH:MM:SS（12/24 小時） |
| 數(shù)據(jù)格式： | YY-MM-DD-dd |
| 接口： | I²C，2 線串口 |
| 電源電壓： | 2.7 V ~ 5.5 V |
| 電壓 - 電源，電池： | 1.8 V ~ 5.5 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 8-TSSOP，8-MSOP（0.118"，3.00mm 寬） |
| 供應商設備封裝： | 8-MSOP |
| 包裝： | 管件 |
4
FN6313.0
June 22, 2006
Hysteresis
SDA and SCL Input Buffer Hysteresis
0.05 x
VDD
V
VOL
SDA Output Buffer LOW Voltage,
Sinking 3mA
00.4
V
Cpin
SDA and SCL Pin Capacitance
TA = 25°C, f = 1MHz, VDD = 5V,
VIN =0V, VOUT = 0V
10
pF
fSCL
SCL Frequency
400
kHz
tIN
Pulse Width Suppression Time at SDA
and SCL Inputs
Any pulse narrower than the max spec
is suppressed.
50
ns
tAA
SCL Falling Edge to SDA Output Data
Valid
SCL falling edge crossing 30% of VDD,
until SDA exits the 30% to 70% of VDD
window.
900
ns
tBUF
Time the Bus Must be Free before the
Start of a New Transmission
SDA crossing 70% of VDD during a
STOP condition, to SDA crossing 70%
of VDD during the following START
condition.
1300
ns
tLOW
Clock LOW Time
Measured at the 30% of VDD crossing.
1300
ns
tHIGH
Clock HIGH Time
Measured at the 70% of VDD crossing.
600
ns
tSU:STA
START Condition Setup Time
SCL rising edge to SDA falling edge.
Both crossing 70% of VDD.
600
ns
tHD:STA
START Condition Hold Time
From SDA falling edge crossing 30% of
VDD to SCL falling edge crossing 70%
of VDD.
600
ns
tSU:DAT
Input daTa Setup Time
From SDA exiting the 30% to 70% of
VDD window, to SCL rising edge
crossing 30% of VDD
100
ns
tHD:DAT
Input Data Hold Time
From SCL falling edge crossing 30% of
VDD to SDA entering the 30% to 70%
of VDD window.
0
900
ns
tSU:STO
STOP Condition Setup Time
From SCL rising edge crossing 70% of
VDD, to SDA rising edge crossing 30%
of VDD.
600
ns
tHD:STO
STOP Condition Hold Time
From SDA rising edge to SCL falling
edge. Both crossing 70% of VDD.
600
ns
tDH
Output Data Hold Time
From SCL falling edge crossing 30% of
VDD, until SDA enters the 30% to 70%
of VDD window.
0ns
tR
SDA and SCL Rise Time
From 30% to 70% of VDD
20 +
0.1 x Cb
300
ns
tF
SDA and SCL Fall Time
From 70% to 30% of VDD
20 +
0.1 x Cb
300
ns
Cb
Capacitive Loading of SDA or SCL
Total on-chip and off-chip
10
400
pF
Rpu
SDA and SCL Bus Pull-up Resistor
Off-chip
Maximum is determined by tR and tF.
For Cb = 400pF, max is about 2~2.5k
.
For Cb = 40pF, max is about 15~20k
1k
NOTES:
2. IRQ and FOUT Inactive.
3. LPMODE = 0 (default).
4. In order to ensure proper timekeeping, the VDD SR- specification must be followed.
5. Typical values are for T = 25°C and 3.3V supply voltage.
6. These are I2C specific parameters and are not directly tested, however they are used during device testing to validate device specification.
7. A write to register 08h should only be done if VDD > VBAT, otherwise the device will be unable to communicate using I
2C.
Serial Interface Specifications
Over the recommended operating conditions unless otherwise specified. (Continued)
SYMBOL
PARAMETER
TEST CONDITIONS
MIN
TYP
(Note 5)
MAX
UNITS
NOTES
ISL1218
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