參數(shù)資料
型號(hào)： ISL12029IVZ
廠商： Intersil
文件頁數(shù)： 20/29頁
文件大小： 0K
描述： IC RTC/CALENDAR EEPROM 14-TSSOP
標(biāo)準(zhǔn)包裝： 960
類型： 時(shí)鐘/日歷
特點(diǎn)： 警報(bào)器，閏年，監(jiān)控器，監(jiān)視計(jì)時(shí)器
時(shí)間格式： HH:MM:SS（12/24 小時(shí)）
數(shù)據(jù)格式： YY-MM-DD-dd
接口： I²C，2 線串口
電源電壓： 2.7 V ~ 5.5 V
電壓 - 電源，電池： 1.8 V ~ 5.5 V
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 14-TSSOP（0.173"，4.40mm 寬）
供應(yīng)商設(shè)備封裝： 14-TSSOP
包裝： 管件
27
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Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
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For information regarding Intersil Corporation and its products, see www.intersil.com
FN6206.10
December 16, 2010
EXAMPLE 2
Pulsed interrupt once per minute (IM = ”1”)
Interrupts at one minute intervals when the seconds register
is at 30 seconds.
A. Set Alarm 0 registers as follows:
B. Set the Interrupt register as follows:
XX indicate other control bits
Once the registers are set, the following waveform will be
seen at IRQ/FOUT:
Note that the status register AL0 bit will be set each time the
alarm is triggered, but does not need to be read or cleared.
ALARM0
REGISTER
BIT
DESCRIPTION
76543210 HEX
SCA0
10110000 B0h Seconds set to 30,
enabled
MNA0
00000000 00h Minutes disabled
HRA0
00000000 00h Hours disabled
DTA0
00000000 00h Date disabled
MOA0
00000000 00h Month disabled
DWA0
00000000 00h Day of week disabled
CONTROL
REGISTER
BIT
DESCRIPTION
76543210 HEX
INT
1 0 1 x x 0 0 0
x0h Enable Alarm and Int
Mode
60s
RTC AND ALARM REGISTERS ARE BOTH 30s
ISL12029, ISL12029A
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