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參數(shù)資料
| 型號： | ISL12029IB27Z-T |
| 廠商： | Intersil |
| 文件頁數(shù)： | 14/29頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC RTC EEPROM LP 2.63V 14-SOIC |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 類型： | 時(shí)鐘/日歷 |
| 特點(diǎn)： | 警報(bào)器，閏年，監(jiān)控器，監(jiān)視計(jì)時(shí)器 |
| 時(shí)間格式： | HH:MM:SS（12/24 小時(shí)） |
| 數(shù)據(jù)格式： | YY-MM-DD-dd |
| 接口： | I²C，2 線串口 |
| 電源電壓： | 2.7 V ~ 5.5 V |
| 電壓 - 電源，電池： | 1.8 V ~ 5.5 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 14-SOIC（0.154"，3.90mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 14-SOICN |
| 包裝： | 標(biāo)準(zhǔn)包裝 |
| 其它名稱： | ISL12029IB27Z-TDKR |
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21
FN6206.10
December 16, 2010
.
Acknowledge Polling
Disabling of the inputs during non-volatile write cycles can
be used to take advantage of the typical 5ms write cycle
time. Once the stop condition is issued to indicate the end of
the master’s byte load operation, the ISL12029 initiates the
internal non-volatile write cycle. Acknowledge polling can
begin immediately. To do this, the master issues a start
condition followed by the Memory Array Slave Address Byte
for a write or read operation (AEh or AFh). If the ISL12029 is
still busy with the non-volatile write cycle then no ACK will be
returned. When the ISL12029 has completed the write
operation, an ACK is returned and the host can proceed with
the read or write operation. Refer to the flow chart in
Figure 24. Note: Do not use the CCR Slave byte (DEh or
DFh) for Acknowledge Polling.
Read Operations
There are three basic read operations: Current Address
Read, Random Read and Sequential Read.
Current Address Read
Internally the ISL12029 contains an address counter that
maintains the address of the last word read incremented by
one. Therefore, if the last read was to address n, the next
read operation would access data from address n + 1. On
power-up, the 16-bit address is initialized to 0h. In this way, a
current address read immediately after the power-on reset
can download the entire contents of memory starting at the
first location. Upon receipt of the Slave Address Byte with
the R/W bit set to one, the ISL12029 issues an
acknowledge, then transmits 8 data bits. The master
terminates the read operation by not responding with an
acknowledge during the ninth clock and issuing a stop
condition. Refer to Figure 23 for the address, acknowledge,
and data transfer sequence.
WORD
ADDRESS 0
S
T
A
R
T
S
T
O
P
SLAVE
ADDRESS
WORD
ADDRESS 1
DATA
(n)
A
C
K
A
C
K
A
C
K
SDA BUS
SIGNALS FROM
THE SLAVE
SIGNALS FROM
THE MASTER
0
DATA
(1)
A
C
K
1
≤ n ≤ 16 FOR EEPROM ARRAY
1
≤ n ≤ 8 FOR CCR
1
0 0 00 00 0
FIGURE 22. PAGE WRITE SEQUENCE
S
T
A
R
T
S
T
O
P
SLAVE
ADDRESS
DATA
A
C
K
SDA BUS
SIGNALS FROM
THE SLAVE
SIGNALS FROM
THE MASTER
1
FIGURE 23. CURRENT ADDRESS READ SEQUENCE
FIGURE 24. ACKNOWLEDGE POLLING SEQUENCE
ACK
RETURNED?
ISSUE MEMORY ARRAY SLAVE
ADDRESS BYTE
AFH (READ) OR AEH (WRITE)
BYTE LOAD
COMPLETED BY
ISSUING STOP.
ENTER ACK POLLING
ISSUE STOP
ISSUE START
NO
YES
ISSUE STOP
NO
CONTINUE
NORMAL READ OR
WRITE COMMAND
SEQUENCE
PROCEED
YES
NON-VOLATILE WRITE
CYCLE COMPLETE. CONTINUE
COMMAND SEQUENCE?
ISL12029, ISL12029A
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| ISL12029IBAZ | 功能描述:實(shí)時(shí)時(shí)鐘 REAL TIME CLKRTC W/ EPROM 4 64VSET 14 RoHS:否 制造商:Microchip Technology 功能:Clock, Calendar. Alarm RTC 總線接口:I2C 日期格式:DW:DM:M:Y 時(shí)間格式:HH:MM:SS RTC 存儲容量:64 B 電源電壓-最大:5.5 V 電源電壓-最小:1.8 V 最大工作溫度:+ 85 C 最小工作溫度: 安裝風(fēng)格:Through Hole 封裝 / 箱體:PDIP-8 封裝:Tube |
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