參數(shù)資料
| 型號： | ISL12027IVZ-T |
| 廠商： | Intersil |
| 文件頁數(shù)： | 25/28頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC RTC/CALENDAR EEPROM 8-TSSOP |
| 產品培訓模塊： | Solutions for Industrial Control Applications |
| 標準包裝： | 2,500 |
| 類型： | 時鐘/日歷 |
| 特點： | 警報器，閏年，監(jiān)控器，監(jiān)視計時器 |
| 時間格式： | HH:MM:SS（12/24 小時） |
| 數(shù)據格式： | YY-MM-DD-dd |
| 接口： | I²C，2 線串口 |
| 電源電壓： | 2.7 V ~ 5.5 V |
| 電壓 - 電源，電池： | 1.8 V ~ 5.5 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 8-TSSOP（0.173"，4.40mm 寬） |
| 供應商設備封裝： | 8-TSSOP |
| 包裝： | 帶卷 (TR) |
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6
FN8232.8
August 12, 2010
tSU:STA START Condition Set-up Time
SCL rising edge to SDA falling edge.
Both crossing 70% of VDD.
600
ns
tHD:STA START Condition Hold Time
From SDA falling edge crossing 30%
of VDD to SCL falling edge crossing
70% of VDD.
600
ns
tSU:DAT Input Data Set-up Time
From SDA exiting the 30% to 70% of
VDD window, to SCL rising edge
crossing 30% of VDD.
100
ns
tHD:DAT Input Data Hold Time
From SCL falling edge crossing 70% of
VDD to SDA entering the 30% to 70%
of VDD window.
0ns
tSU:STO STOP Condition Set-up Time
From SCL rising edge crossing 70% of
VDD, to SDA rising edge crossing 30%
of VDD.
600
ns
tHD:STO STOP Condition Hold Time for
Read, or Volatile Only Write
From SDA rising edge to SCL falling
edge. Both crossing 70% of VDD.
600
ns
tDH
Output Data Hold Time
From SCL falling edge crossing 30% of
VDD, until SDA enters the 30% to 70%
of VDD window.
0ns
tR
SDA and SCL Rise Time
From 30% to 70% of VDD
20 +
0.1xCb
250
ns
tF
SDA and SCL Fall Time
From 70% to 30% of VDD
20 +
0.1xCb
250
ns
Cpin
SDA, and SCL Pin Capacitance
10
pF
tWC
Non-Volatile Write Cycle Time
12
20
ms
14
tR
SDA and SCL Rise Time
From 30% to 70% of VDD
20 +
0.1xCb
250
ns
15
tF
SDA and SCL Fall Time
From 70% to 30% of VDD
20 +
0.1xCb
250
ns
15
Cb
Capacitive Loading of SDA or SCL Total on-chip and off-chip
10
400
pF
15
RPU
SDA and SCL Bus Pull-up Resistor
Off-chip
Maximum is determined by tR and tF.
For Cb = 400pF, max is about
2k
Ω~2.5kΩ.
For Cb = 40pF, max is about
15k
Ω~20kΩ
1k
Ω
15
NOTES:
7. RESET Inactive (no reset).
8. VIL = VDD x 0.1, VIH = VDD x 0.9, fSCL = 400kHz.
9. VRESET = 2.63V (VDD must be greater than VRESET), VBAT = 0V.
10. Bit BSW = 0 (Standard Mode), ATR = 00h, VBAT ≥1.8V.
11. Specified at +25°C.
12. In order to ensure proper timekeeping, the VDD SR- specification must be followed.
13. Parameter is not 100% tested.
14. tWC is the minimum cycle time to be allowed for any non-volatile Write by the user, it is the time from valid STOP condition at the end of Write
sequence of a serial interface Write operation, to the end of the self-timed internal non-volatile write cycle.
15. These are I2C specific parameters and are not directly tested, however they are used during device testing to validate device specification.
16. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by
characterization and are not production tested.
Serial Interface (I2C) Specifications (Continued)
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
NOTES
ISL12027, ISL12027A
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