參數(shù)資料
型號(hào): ISL12027AIV27Z-T
廠商: INTERSIL CORP
元件分類(lèi): 時(shí)鐘/數(shù)據(jù)恢復(fù)及定時(shí)提取
英文描述: REAL TIME CLOCK, PDSO8
封裝: ROHS COMPLIANT, MO-153AC, TSSOP-8
文件頁(yè)數(shù): 19/28頁(yè)
文件大?。?/td> 384K
代理商: ISL12027AIV27Z-T
26
FN8232.8
August 12, 2010
Alarm Operation Examples
Following are examples of both Single Event and periodic
Interrupt Mode alarms.
EXAMPLE 1
Alarm 0 set with single interrupt (IM=”0”)
A single alarm will occur on January 1 at 11:30am.
A. Set Alarm 0 registers as follows:
B. Also the AL0E bit must be set as follows:
After these registers are set, an alarm will be generated when
the RTC advances to exactly 11:30am on January 1 (after
seconds changes from 59 to 00) by setting the AL0 bit in the
status register to “1”.
EXAMPLE 2
Pulsed interrupt once per minute (IM = ”1”)
Interrupts at one minute intervals when the seconds register
is at 30s.
A. Set Alarm 0 registers as follows:
B. Set the Interrupt register as follows:
Note that the status register AL0 bit will be set each time the
alarm is triggered, but does not need to be read or cleared.
ALARM0
REGISTER
BIT
DESCRIPTION
76
543210
HEX
SCA0
00 000000
00h Seconds disabled
MNA0
10 110000
B0h Minutes set to 30,
enabled
HRA0
1 0 010001
91h Hours set to 11,
enabled
DTA0
10 000001
81h Date set to 1,
enabled
MOA0
10 000001
81h Month set to 1,
enabled
DWA0
00 000000
00h Day of week
disabled
CONTROL
REGISTER
BIT
DESCRIPTION
7654
3210
HEX
INT
0010 0000
x0hEnable Alarm
ALARM0
REGISTER
BIT
DESCRIPTION
76543210 HEX
SCA0
10110000 B0h Seconds set to 30,
enabled
MNA0
00000000 00h Minutes disabled
HRA0
00000000 00h Hours disabled
DTA0
00000000 00h Date disabled
MOA0
00000000 00h Month disabled
DWA0
00000000 00h Day of week disabled
CONTROL
REGISTER
BIT
DESCRIPTION
76543210 HEX
INT
10100000 x0hEnable Alarm and Int
Mode
ISL12027, ISL12027A
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