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參數(shù)資料
| 型號： | ISL12023IVZ |
| 廠商： | Intersil |
| 文件頁數(shù)： | 6/29頁 |
| 文件大小： | 0K |
| 描述： | IC RTC/CLDR TEMP SNSR 14-TSSOP |
| 產(chǎn)品培訓(xùn)模塊： | Solutions for Industrial Control Applications |
| 標準包裝： | 960 |
| 類型： | 時鐘/日歷 |
| 特點： | 警報器，夏令時，閏年，SRAM |
| 存儲容量： | 128B |
| 時間格式： | HH:MM:SS（12/24 小時） |
| 數(shù)據(jù)格式： | YY-MM-DD-dd |
| 接口： | I²C，2 線串口 |
| 電源電壓： | 2.7 V ~ 5.5 V |
| 電壓 - 電源，電池： | 1.8 V ~ 5.5 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 14-TSSOP（0.173"，4.40mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 14-TSSOP |
| 包裝： | 管件 |
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ISL12023
14
FN6682.3
December 6, 2011
Example - When the LBAT85 Remains at “0” In Battery
Mode:
If the device enters into battery mode after the minute register
reaches 20h and switches back to Normal Mode before the
minute register reaches 29h, then the LBAT85 bit will remain at
“0” the next time the device switches back to Normal Mode.
LOW BATTERY INDICATOR 75% BIT (LBAT75)
In Normal Mode (VDD), this bit indicates when the battery level
has dropped below the pre-selected trip levels. The trip points are
selected by three bits: VB75Tp2, VB75Tp1 and VB75Tp0 in the
PWR_VBAT registers. The LBAT75 detection happens
automatically once every minute when seconds register reaches
59. The detection can also be manually triggered by setting the
TSE bit in BETA register to “1”. The LBAT75 bit is set when the
VBAT has dropped below the pre-selected trip level, and will self
clear when the VBAT is above the pre-selected trip level at the
next detection cycle either by manual or automatic trigger.
In Battery Mode (VBAT), this bit indicates the device has entered
into battery mode by polling once every 10 minutes. The LBAT85
detection happens automatically once when the minute register
reaches x9h or x0h minutes.
Example - When the LBAT75 is Set to “1” in Battery Mode:
The minute register changes to 30h when the device is in battery
mode, the LBAT75 is set to “1” the next time the device switches
back to Normal Mode.
Example - When the LBAT75 Remains at “0” in Battery Mode:
If the device enters into battery mode after the minute register
reaches 49h and switches back to Normal Mode before minute
register reaches 50h, then the LBAT75 bit will remain at “0” the
next time the device switches back to Normal Mode.
REAL TIME CLOCK FAIL BIT (RTCF)
This bit is set to a “1” after a total power failure. This is a read
only bit that is set by hardware (ISL12023 internally) when the
device powers up after having lost all power (defined as VDD = 0V
and VBAT = 0V). The bit is set regardless of whether VDD or VBAT
is applied first. The loss of only one of the supplies does not set
the RTCF bit to “1”. The first valid write to the RTC section after a
complete power failure resets the RTCF bit to “0” (writing one
byte is sufficient).
Interrupt Control Register (INT)
AUTOMATIC RESET BIT (ARST)
This bit enables/disables the automatic reset of the ALM, LVDD,
LBAT85, and LBAT75 status bits only. When ARST bit is set to “1”,
these status bits are reset to “0” after a valid read of the
respective status register (with a valid STOP condition). When the
ARST is cleared to “0”, the user must manually reset the ALM,
LVDD, LBAT85, and LBAT75 bits.
WRITE RTC ENABLE BIT (WRTC)
The WRTC bit enables or disables write capability into the RTC
Timing Registers. The factory default setting of this bit is “0”.
Upon initialization or power up, the WRTC must be set to “1” to
enable the RTC. Upon the completion of a valid write (STOP), the
RTC starts counting. The RTC internal 1Hz signal is synchronized
to the STOP condition during a valid write cycle.
INTERRUPT/ALARM MODE BIT (IM)
This bit enables/disables the interrupt mode of the alarm
function. When the IM bit is set to “1”, the alarm will operate in
the interrupt mode, where an active low pulse width of 250ms
will appear at the IRQ pin when the RTC is triggered by the alarm
as defined by the alarm registers (0Ch to 11h). When the IM bit is
cleared to “0”, the alarm will operate in standard mode, where
the IRQ pin will be set low until the ALM status bit is cleared to
“0”.
FREQUENCY OUTPUT AND INTERRUPT BIT (FOBATB)
This bit enables/disables the FOUT and IRQ pins during battery-
backup mode (i.e. VBAT power source active). When the FOBATB
is set to “1” the FOUT and IRQ pins are disabled during battery-
backup mode. This means that both the frequency output and
alarm output functions are disabled. When the FOBATB is cleared
to “0”, the FOUT and IRQ pins are enabled during battery-backup
mode. Note that the open drain FOUT and IRQ pins will need a
pullup to the battery voltage to operate in battery-backup mode.
FREQUENCY OUT CONTROL BITS (FO<3:0>)
These bits enable/disable the frequency output function and
frequency selection.
TABLE 3. INTERRUPT CONTROL REGISTER (INT)
ADDR
7
6
5
4
321
0
08h
ARST
WRTC
IM
FOBATB
FO3 FO2 FO1 FO0
TABLE 4.
IM BIT
INTERRUPT/ALARM FREQUENCY
0
Single Time Event Set By Alarm
1
Repetitive/Recurring Time Event Set By Alarm
TABLE 5. FREQUENCY SELECTION OF FOUT PIN
FREQUENCY,
FOUT
UNITS
FO3
FO2
FO1
FO0
0
Hz
0
000
32768
Hz
0
001
4096
Hz
0
1
0
1024
Hz
0
011
64
Hz
0
100
32
Hz
0
101
16
Hz
0
110
8
Hz
0
111
4
Hz
1
000
2
Hz
1
001
1
Hz
1
010
1/2
Hz
1
011
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