2 FN6668.9 June 20, 2012 Block Diagram Pin Configuration ISL12022M (20 LD SOIC) TOP VIEW I2
參數(shù)資料
型號(hào)： ISL12022MIBZ-T7A
廠商： Intersil
文件頁(yè)數(shù)： 12/31頁(yè)
文件大?。?/td> 0K
描述： IC RTC/CALENDAR TEMP SNSR 20SOIC
應(yīng)用說(shuō)明： Addressing Power Issues in Real Time Clock Appls
產(chǎn)品培訓(xùn)模塊： Solutions for Industrial Control Applications
標(biāo)準(zhǔn)包裝： 250
類型： 時(shí)鐘/日歷
特點(diǎn)： 警報(bào)器，夏令時(shí)，閏年，SRAM
存儲(chǔ)容量： 128B
時(shí)間格式： HH:MM:SS（12/24 小時(shí)）
數(shù)據(jù)格式： YY-MM-DD-dd
接口： I²C，2 線串口
電源電壓： 2.7 V ~ 5.5 V
電壓 - 電源，電池： 1.8 V ~ 5.5 V
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 20-SOIC（0.295"，7.50mm 寬）
供應(yīng)商設(shè)備封裝： 20-SOIC
包裝： 帶卷 (TR)
ISL12022M
2
FN6668.9
June 20, 2012
Block Diagram
Pin Configuration
ISL12022M
(20 LD SOIC)
TOP VIEW
I2C
INTERFACE
CONTROL
LOGIC
ALARM
FREQUENCY
OUT
RTC
DIVIDER
SDA
BUFFER
CRYSTAL
OSCILLATOR
POR
SWITCH
SCL
BUFFER
SDA
SCL
VDD
VBAT
INTERNAL
SUPPLY
VTRIP
SECONDS
MINUTES
HOURS
DAY OF WEEK
DATE
MONTH
YEAR
USER
SRAM
CONTROL
REGISTERS
GND
REGISTERS
TEMPERATURE
SENSOR
FREQUENCY
CONTROL
IRQ/FOUT
+
-
NC
GND
NC
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
NC
GND
VDD
NC
GND
VBAT
NC
IRQ/FOUT
SCL
SDA
Pin Descriptions
PIN NUMBER
SYMBOL
DESCRIPTION
1, 2, 3, 4, 5, 9,
10, 16, 17, 18,
19, 20
NC
No Connection. Do not connect to a signal or supply voltage.
7VBAT
Backup Supply. This input provides a backup supply voltage to the device. VBAT supplies power to the device in the event
that the VDD supply fails. This pin can be connected to a battery, a supercapacitor or tied to ground if not used. See the
Battery Monitor parameter in “DC Operating Characteristics RTC” on page 5. This pin should be tied to ground if not used.
11
SDA
Serial Data. SDA is a bi-directional pin used to transfer data into and out of the device. It has an open drain output and
may be OR’ed with other open drain or open collector outputs. The input buffer is always active (not gated) in normal
mode.
An open drain output requires the use of a pull-up resistor. The output circuitry controls the fall time of the output signal
with the use of a slope controlled pull-down. The circuit is designed for 400kHz I2C interface speeds. It is disabled when
the backup power supply on the VBAT pin is activated.
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