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參數(shù)資料
型號: ISL12022IBZ-T7A
廠商: Intersil
文件頁數(shù): 21/29頁
文件大?。?/td> 0K
描述: IC RTC/CALENDAR TEMP SNSR 8SOIC
應(yīng)用說明: Addressing Power Issues in Real Time Clock Appls
產(chǎn)品培訓(xùn)模塊: Solutions for Industrial Control Applications
標(biāo)準(zhǔn)包裝: 250
類型: 時鐘/日歷
特點: 警報器,夏令時,閏年,SRAM
存儲容量: 128B
時間格式: HH:MM:SS(12/24 小時)
數(shù)據(jù)格式: YY-MM-DD-dd
接口: I²C,2 線串口
電源電壓: 2.7 V ~ 5.5 V
電壓 - 電源,電池: 1.8 V ~ 5.5 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 8-SOIC(0.154",3.90mm 寬)
供應(yīng)商設(shè)備封裝: 8-SOIC
包裝: 帶卷 (TR)
ISL12022
28
Intersil products are manufactured, assembled and tested utilizing ISO9000 quality systems as noted
in the quality certifications found at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time
without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be
accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third
parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
FN6659.3
November 22, 2011
For additional products, see www.intersil.com/product_tree
Temperature Compensation Operation
The ISL12022 temperature compensation feature needs to be
enabled by the user. This must be done in a specific order as
follows.
1. Read register 0Dh, the BETA register. This register contains the
5-bit BETA trimmed value which is automatically loaded on initial
power-up. Mask off the 5LSB’s of the value just read.
2. Bit 7 of the BETA register is the master enable control for
temperature sense operation. Set this to “1” to allow
continuous temperature frequency correction. Frequency
correction will then happen every 60s with VDD applied.
3. Bits 5 and 6 of the BETA register control temperature
compensation in battery-backup mode (see Table 15). Set the
values for the operation desired.
4. Write back to register 0Dh making sure not to change the 5
LSB values, and include the desired compensation control bits.
Note that every time the BETA register is written with the TSE
bit = 1, a temperature compensation cycle is instigated and a
new correction value will be loaded into the FATR/FDTR registers
(if the temperature changed since the last conversion).
Also note that registers 0Bh and 0Ch, the ITR0 and ALPHA
registers, should not be changed. If they must be written be sure
to write the same values that are recalled from initial power-up.
The ITR0 register may be written if the user wishes to re-calibrate
the oscillator frequency at room temperature for aging or board
mounting. The original recalled value can be re-written if desired
after testing.
For further information on the operation of the ISL12022 and
temperature compensated RTC’s, see Intersil Application Note
AN1389, “Using Intersil’s High Accuracy Real Time Clock
Daylight Savings Time (DST) Example
DST involves setting the forward and back times and allowing the
RTC device to automatically advance the time or set the time back.
This can be done for current year, and future years. Many regions
have DST rules that use standard months, weeks and time of the
day which permit a pre-programmed, permanent setting.
Table 27 shows the example setup for the ISL12022.
The Enable bit (DSTE) is in the Month forward register, so the BCD
value for that register is altered with the additional bit. The Week
and Day values along with Week/Day vs Date select bit is in the
Week/Day register, so that value is also not straight BCD. Hour
and Month are normal BCD, but the Hour doesn’t use the MIL bit
since Military time PM values are already discretely different
from AM/PM time PM values. The DST reverse setting utilizes the
option to select the last week of the month for October, which
could have 4 or 5 weeks but needs to have the time change on
the last Sunday.
Note that the DSTADJ bit in the status register monitors whether
the DST forward adjustment has happened. When it is “1”, DST
forward has taken place. When it is “0”, then either DST reverse
has happened, or it has been reset either by initial power-up or if
the DSTE bit has been set to “0”.
TABLE 27. DST EXAMPLE
VARIABLE
VALUE
REGISTER VALUE
Month Forward and DST Enable
April
15h
84h
Week and Day Forward and select
Day/Week, not Date
1st Week and
Sunday
16h
48h
Date Forward
not used
17h
00h
Hour Forward
2am
18h
02h
Month Reverse
October
19h
10h
Week and Day Reverse and select
Day/Week, not Date
Last Week and
Sunday
1Ah
78h
Date Reverse
not used
1Bh
00h
Hour Reverse
2am
1Ch
02h
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