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| 型號： | ISL12020MIRZ-T7A |
| 廠商： | Intersil |
| 文件頁數(shù)： | 21/34頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC RTC/CALENDAR TEMP SNSR 20DFN |
| 產(chǎn)品培訓(xùn)模塊： | Solutions for Industrial Control Applications |
| 標(biāo)準(zhǔn)包裝： | 250 |
| 類型： | 時鐘/日歷 |
| 特點： | 警報器，夏令時，閏年，SRAM |
| 存儲容量： | 128B |
| 時間格式： | HH:MM:SS（12/24 小時） |
| 數(shù)據(jù)格式： | YY-MM-DD-dd |
| 接口： | I²C，2 線串口 |
| 電源電壓： | 2.7 V ~ 5.5 V |
| 電壓 - 電源，電池： | 1.8 V ~ 5.5 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 20-LFDFN 裸露焊盤 |
| 供應(yīng)商設(shè)備封裝： | 20-DFN（5.5x4.0） |
| 包裝： | 帶卷 (TR) |
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ISL12020M
28
FN6667.5
December 13, 2011
Application Section
Power Supply Considerations
The ISL12022M contains programmed EEPROM registers which
are recalled to volatile RAM registers during initial powerup.
These registers contain DC voltage, frequency and temperature
calibration settings. Initial powerup can be either application of
VBAT or VDD power, whichever is first. It is important that the
initial powerup meet the power supply slew rate specification to
avoid faulty EEPROM powerup recall. Also, any glitches or low
voltage DC pauses should be avoided, as these may activate
recall at a low voltage and load erroneous data into the
calibration registers. Note that a very slow Vdd ramp rate
(outside data sheet limits) will almost always trigger erroneous
recall and should be avoided entirely.
Battery-Backup Details
The ISL12020M has automatic switchover to battery-backup
when the VDD drops below the VBAT mode threshold. A wide
variety of backup sources can be used, including standard and
rechargeable lithium, Super Capacitors, or regulated secondary
sources. The serial interface is disabled in battery-backup, while
the oscillator and RTC registers are operational. The SRAM
register contents are powered to preserve their contents as well.
The input voltage range for VBAT is 1.8V to 5.5V, but keep in
mind the temperature compensation only operates for VBAT >
2.7V. Note that the device is not guaranteed to operate with a
VBAT < 1.8V, so the battery should be changed before
discharging to that level. It is strongly advised to monitor the low
battery indicators in the status registers and take action to
replace discharged batteries.
If a Super Capacitor is used, it is possible that it may discharge to
below 1.8V during prolonged power-down. Once powered up, the
device may lose serial bus communications until both VDD and
VBAT are powered down together. To avoid that situation,
including situations where a battery may discharge deeply, the
circuit in Figure 21 can be used.
The diode, DBAT will add a small drop to the battery voltage but
will protect the circuit should battery voltage drop below 1.8V.
The jumper is added as a safeguard should the battery ever need
to be disconnect from the circuit.
.
The VDD negative slew rate should be limited to below the data
sheet spec (10V/ms) otherwise battery switchover can be
delayed, resulting in SRAM contents corruption and oscillator
operation interruption.
Some applications will require separate supplies for the RTC VDD
and the I2C pullups. This is not advised, as it may compromise
the operation of the I2C bus. For applications that do require
serial bus communication with the RTC VDD powered down, the
SDA pin must be pulled low during the time the RTC VDD ramps
down to 0V. Otherwise, the device may lose serial bus
communications once VDD is powered up, and will return to
normal operation ONLY once VDD and VBAT are both powered
down together.
Layout Considerations
The ISL12020M contains a quarts crystal and requires special
handling during PC board assembly. Excessive shock and vibrations
should be avoided. Ultrasound cleaning is not advisable. See Note 7
on page 6 in the electrical specifications table pertaining to solder
reflow effects on oscillator accuracy.
The crystal pins X1 and X2 have a very high impedance, and
oscillator circuits operating at low frequencies (such as 32.768kHz)
are known to pick up noise very easily if layout precautions are not
followed. Most instances of erratic clocking or large accuracy errors
can be traced to the susceptibility of the oscillator circuit to
interference from adjacent high speed clock or data lines. Careful
layout of the RTC circuit will avoid noise pickup and insure accurate
clocking.
Figure 22 shows a suggested layout for the ISL12020M device.
Three main precautions should be followed:
1. Do not run the serial bus lines or any high speed logic lines in
the vicinity of the X1 and X2 pins. These logic level lines can
induce noise in the oscillator circuit, causing misclocking.
FIGURE 20. READ SEQUENCE (CSR SLAVE ADDRESS SHOWN)
SIGNALS
FROM THE
MASTER
SIGNALS FROM
THE SLAVE
SIGNAL AT
SDA
S
T
A
R
T
IDENTIFICATION
BYTE WITH
R/W = 0
ADDRESS
A
C
K
A
C
K
0
S
T
O
P
A
C
K
1
IDENTIFICATION
BYTE WITH
R/W = 1
A
C
K
S
T
A
R
T
LAST READ
DATA BYTE
FIRST READ
DATA BYTE
A
C
K
10
1
1111
10
1
11 11
FIGURE 21. SUGGESTED BATTERY-BACKUP CIRCUIT
DBAT
CBAT
CIN
BAT43W
0.1F
VDD = 2.7V
TO 5.5V
VBAT = 1.8V
TO 3.2V
JBAT
ISL12020M
VDD
GND
VBAT
+
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ISL12021 | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:Real Time Clock with On Chip Temp Compensation 【5ppm |
| ISL12021CVZ | 功能描述:IC RTC LP BATT BACK SRAM 14TSSOP RoHS:是 類別:集成電路 (IC) >> 時鐘/計時 - 實時時鐘 系列:- 產(chǎn)品培訓(xùn)模塊:Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:1 系列:- 類型:時鐘/日歷 特點:警報器，閏年，SRAM 存儲容量:- 時間格式:HH:MM:SS（12/24 小時） 數(shù)據(jù)格式:YY-MM-DD-dd 接口:SPI 電源電壓:2 V ~ 5.5 V 電壓 - 電源，電池:- 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:8-WDFN 裸露焊盤 供應(yīng)商設(shè)備封裝:8-TDFN EP 包裝:管件 |
| ISL12021IVZ | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:Real Time Clock with On Chip Temp Compensation 【5ppm |
| ISL12022 | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:Real Time Clock with On Chip ±5ppm Temp Compensation |
| ISL12022IBZ | 功能描述:實時時鐘 REAL TIME CLK/CLNDR W/TEMP COMP 8 L RoHS:否 制造商:Microchip Technology 功能:Clock, Calendar. Alarm RTC 總線接口:I2C 日期格式:DW:DM:M:Y 時間格式:HH:MM:SS RTC 存儲容量:64 B 電源電壓-最大:5.5 V 電源電壓-最小:1.8 V 最大工作溫度:+ 85 C 最小工作溫度: 安裝風(fēng)格:Through Hole 封裝 / 箱體:PDIP-8 封裝:Tube |
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