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參數(shù)資料
| 型號(hào)： | ISL12008IB8Z |
| 廠商： | Intersil |
| 文件頁數(shù)： | 3/19頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC RTC I2C LO-POWER 8-SOIC |
| 標(biāo)準(zhǔn)包裝： | 980 |
| 類型： | 時(shí)鐘/日歷 |
| 特點(diǎn)： | 警報(bào)器，閏年 |
| 時(shí)間格式： | HH:MM:SS:hh（24 小時(shí)） |
| 數(shù)據(jù)格式： | YY-MM-DD-dd |
| 接口： | I²C，2 線串口 |
| 電源電壓： | 2.7 V ~ 5.5 V |
| 電壓 - 電源，電池： | 1.8 V ~ 5.5 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 8-SOIC（0.154"，3.90mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 8-SOIC |
| 包裝： | 管件 |
11
FN6690.1
September 26, 2008
LEAP YEARS
Leap years add the day February 29 and are defined as those
years that are divisible by 4. Years divisible by 100 are not leap
years, unless they are also divisible by 400. This means that
the year 2000 is a leap year, the year 2100 is not. The
ISL12008 does not correct for the leap year in the year 2100.
Control and Status Registers
Addresses [07h to 0Bh]
The Control and Status Registers consist of the Status
Register, Interrupt and Alarm Register, Analog Trimming and
Digital Trimming Registers.
Status Register (SR) [Address 0Bh]
The Status Register is located in the memory map at
address 0Bh. This is a volatile register that provides either
control or status of RTC failure, battery mode, alarm trigger,
crystal oscillator status, ReSeal and auto reset of status
bits.
REAL TIME CLOCK FAIL BIT (RTCF)
This bit is set to a “1” after a total power failure. This is a read
only bit that is set by hardware (ISL12008 internally) when
the device powers up after having lost all power to the device
(both VDD and VBAT go to 0V). The bit is set regardless of
whether VDD or VBAT is applied first. The loss of only one of
the supplies does not set the RTCF bit to “1”. On power-up
after a total power failure, all registers are set to their default
states and the clock will not increment until at least one byte
is written to the clock register. The first valid write to the RTC
section after a complete power failure resets the RTCF bit to
“0” (writing one byte is sufficient).
BATTERY BIT (BAT)
This bit is set to a “1” when the device enters battery backup
mode. This bit can be reset either manually by the user or
automatically reset by enabling the auto-reset bit (see ARST
bit). A write to this bit in the SR can only set it to “0”, not “1”.
ALARM BIT (ALM)
These bits announce if the alarm matches the real time
clock. If there is a match, the respective bit is set to “1”. This
bit can be manually reset to “0” by the user or automatically
reset by enabling the auto-reset bit (see ARST bit). A write to
this bit in the SR can only set it to “0”, not “1”.
NOTE: An alarm bit that is set by an alarm occurring during an SR
read operation will remain set after the read operation is complete.
ReSeal (RESEAL)
The ReSeal enables the device enter into the InterSeal
Battery Saver mode after manufacture testing for board
functionality. The factory default setting of this bit is “0”. The
RESEAL must be set to “0” to enable the battery function
during normal operation or full functional testing. To use the
ReSeal function, simply set RESEAL bit to “1” after the
testing is completed. It will enable the InterSeal Battery
Saver mode and prevents battery current drain before it is
first used.
AUTO RESET ENABLE BIT (ARST)
This bit enables/disables the automatic reset of the BAT,
ALM and TMR status bits only. When ARST bit is set to “1”,
these status bits are reset to “0” after a valid read of the
respective status register (with a valid STOP condition).
When the ARST is cleared to “0”, the user must manually
reset the BAT and ALM bits.
Interrupt Control Register (INT) [Address 08h]
LOW POWER MODE BIT (LPMODE)
This bit enables/disables low power mode. With
LPMODE = “0”, the device will be in normal mode and the
VBAT supply will be used when VDD < VBAT - VBATHYS and
VDD < VTRIP. With LPMODE = “1”, the device will be in low
power mode and the VBAT supply will be used when
VDD < VBAT -VBATHYS. There is a supply current saving of
about 600nA when using LPMODE = “1” with VDD = 5V.
with LPMODE ON and OFF.)
ALARM ENABLE BIT (ALME)
This bit enables/disables the alarm function. When the ALME
bit is set to “1”, the alarm function is enabled. When the ALME
bit is cleared to “0”, the alarm function is disabled. ALME bit is
set to “0” at power-up.
Oscillator Fail Register (OF) [Address 09h]
OSCILLATOR FAIL BIT (OF)
This bit is set to a “1” when the X1 pin has no oscillation.
This bit can be reset when the X1 has crystal oscillation and
a write to “0”. This bit can only be written as “0” and not as a
“1”. The OF bit is set to “1” at power up from a complete
power down (VDD and VBAT are removed). Address 1, bit 7
TABLE 2. STATUS REGISTER (SR)
ADDR
7
6
5
4
3
2
1
0
0Bh
ARST
0
RESEAL
0
ALM BAT RTCF
Default
0
1
TABLE 3. INTERRUPT CONTROL REGISTER (INT)
ADDR
7
6
5
4
3210
08h
0
ALME
LPMODE
0
0000
Default
0
0000
TABLE 4. INTERRUPT CONTROL REGISTER (INT)
ADDR
7
6543210
09h
OF
000
0000
Default
1
0000000
ISL12008
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| ISL12008IB8Z-T | 功能描述:實(shí)時(shí)時(shí)鐘 LW PWR RTC W/RESEAL 8LD RoHS:否 制造商:Microchip Technology 功能:Clock, Calendar. Alarm RTC 總線接口:I2C 日期格式:DW:DM:M:Y 時(shí)間格式:HH:MM:SS RTC 存儲(chǔ)容量:64 B 電源電壓-最大:5.5 V 電源電壓-最小:1.8 V 最大工作溫度:+ 85 C 最小工作溫度: 安裝風(fēng)格:Through Hole 封裝 / 箱體:PDIP-8 封裝:Tube |
| ISL12020 | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:Low Power RTC with VDD Battery Backed SRAM and Embedded Temp Compensation 【5ppm with Auto Day Light Saving |
| ISL12020CBZ | 制造商:Rochester Electronics LLC 功能描述: 制造商:Intersil Corporation 功能描述: |
| ISL12020IBZ | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:Low Power RTC with VDD Battery Backed SRAM and Embedded Temp Compensation 【5ppm with Auto Day Light Saving |
| ISL12020M | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:Low Power RTC with Battery Backed SRAM, Integrated ±5ppm Temperature Compensation and Auto Daylight Saving |
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