Publication Release Date: Oct 31 2008 - 9 - Revision 1.2 PIN NAME PDIP/SOIC TSOP FUNCTION RAC 24 3 Row Address Clock : RA" />
參數(shù)資料
型號: ISD5008EYI
廠商: Nuvoton Technology Corporation of America
文件頁數(shù): 54/54頁
文件大?。?/td> 0K
描述: IC VOICE REC/PLAY 4-8MIN 28-TSOP
標(biāo)準(zhǔn)包裝: 234
系列: ISD5008
接口: SPI/Microwire
濾波器通頻帶: 1.7 ~ 3.4kHz
持續(xù)時間: 4-8 分鐘
安裝類型: 表面貼裝
封裝/外殼: 28-TSSOP(0.465",11.8mm 寬)
供應(yīng)商設(shè)備封裝: 28-TSOP
配用: ISD-ES511-ND - EVALUATION SYSTEM FOR ISD5100
ISD-ES501-ND - EVALUATION SYSTEM FOR ISD5008
ISD5008
Publication Release Date: Oct 31 2008
- 9 -
Revision 1.2
PIN NAME
PDIP/SOIC
TSOP
FUNCTION
RAC
24
3
Row Address Clock
: RAC is an open drain output pin that
marks the end of a row. At the 8 kHz sampling frequency, the
duration of this period is 200 ms. There are 1,200 rows of
memory in the ISD5008 devices. RAC stays HIGH for 175 ms
and stays LOW for the remaining 25 ms before it reaches the
end of the row.
At the 8 kHz sampling frequency, the RAC pin remains HIGH
for 109.38 sec and stays LOW for 15.63 sec under the
Message Cueing mode. See Table 15 Timing Parameters for
RAC timing information at other sample rates. When a record
command is first initiated, the RAC pin remains HIGH for an
extra TRACLO period, to load sample and hold circuits internal to
the device. The RAC pin can be used for message
management techniques.
A pull-up resistor is required to connect this pin to other device.
25
4
Interrupt
:
INT
is an open drain output pin. The ISD5008
interrupt pin goes LOW and stays LOW when an Overflow
(OVF), or End of Message (EOM) marker or Message Cueing
is detected. The interrupt is cleared the next time an SPI cycle
is completed. The interrupt status can be read by a RINT
instruction that will give one of the two flags out the MISO line.
A pull-up resistor is required to connect this pin to other device.
OVF Flag
. The overflow flag indicates that the end of the
ISD5008’s analog memory has been reached during a record
or playback operation.
EOM Flag.
The end of message flag is set only during
playback, when an EOM is found. There are eight possible
EOM markers per row.
XCLK
26
5
External Clock
: The external clock input has an internal pull-
down device. Normally, the ISD5008 is operated at one of four
internal rates selected for its internal oscillator by the Sample
Rate Select bits. If greater precision is required, the device can
be clocked through the XCLK pin as described in Table 2.
Because the anti-alising and smoothing filters track the Sample
Rate Select bits, one must, for optimum performance, change
the external clock AND the Sample Rate Configuration bits to
one of the four values properly to set the filters to the correct
cutoff frequency as described in Table 1. The duty cycle on the
input clock is not critical, as the clock is immediately divided by
two internally. If the XCLK is not used, this input should be
connected to VSSD.
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ISD5008SERIES 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Single-Chip Voice Record/Playback Device