參數(shù)資料
型號(hào): ISD-SR3000
文件頁數(shù): 66/120頁
文件大?。?/td> 1293K
代理商: ISD-SR3000
2-25
2—SOFTWARE
ISD-SR3000
ISD
CFG
Configure ISD-SR3000
Opcode:
Syntax:
Type:
Description:
0x01
CFG config_value
Synchronous
Configures the ISD-SR3000 processor for various hardware environments. It
should be used to change the default ISD-SR3000 processor configuration.
The config_value parameter is a 24-bit word and is encoded as follows.
Parameters:
BIT
3 - 0
DESCRIPTION (the sign “X” refers to a don’t care)
Memory type
15 - 4
16
Reserved.
Clock bit rate
0: One bit rate clock (default)
1: Two bit rate clock.
CODEC configuration
0: Short-frame format (default)
1: Long-frame format (guaranteed by design, but not tested).
CODEC type
Bits
17
19 - 18
Bits
3
0
1
All other
2
0
0
1
0
0
0
0
0
Settings
No Memory
AMD’s AM29F800/AM29F160 Flash (default)
Reserved
Bits
19
18
0
1
0
1
Settings
16-bit linear
μ-Law (default)
A-Law
Reserved
0
0
1
1
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