參數(shù)資料
型號: IS93C56A-3ZLA3
廠商: INTEGRATED SILICON SOLUTION INC
元件分類: DRAM
英文描述: 2K-BIT/4K-BIT SERIAL ELECTRICALLY ERASABLE PROM
中文描述: 128 X 16 MICROWIRE BUS SERIAL EEPROM, PDSO8
封裝: 0.169 INCH, LEAD FREE, MO-153, TSSOP-8
文件頁數(shù): 14/16頁
文件大?。?/td> 136K
代理商: IS93C56A-3ZLA3
PACKAGING INFORMATION
ISSI
Integrated Silicon Solution, Inc. — www.issi.com —
1-800-379-4774
Rev. D
02/14/03
Copyright 2003 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time
without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to
obtain the latest version of this device specification before relying on any published information and before placing orders for products.
300-mil Plastic DIP
Package Code: N,P
A
D
1
B
N
SEATING PLANE
C
A1
eA
L
e
B1
S
E1
E
S
FOR
32-PIN ONLY
B2
MILLIMETERS
INCHES
Sym.
Min.
Max.
Min.
Max.
N0.
Leads
8
A
A1
B
B1
B2
C
D
E
E1
3.68
0.38
0.36
1.14
0.81
0.20
9.12
7.62
6.20
4.57
0.56
1.52
1.17
0.33
9.53
8.26
6.60
0.145
0.015
0.014
0.045
0.032
0.008
0.359
0.300
0.244
0.180
0.022
0.060
0.046
0.013
0.375
0.325
0.260
eA
e
8.13
9.65
0.320
0.380
2.54 BSC
0.100 BSC
L
S
3.18
0.64
0.125
0.025
0.762
0.030
Notes:
1. Controlling dimension: inches, unless otherwise specified.
2. BSC = Basic lead spacing between centers.
3. Dimensions D and E1 do not include mold flash protrusions and
should
be measured from the bottom of the package
.
4. Formed leads shall be planar with respect to one another within 0.004
inches at the seating plane.
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