- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄377579 > IS93C56-3 (Integrated Silicon Solution, Inc.) 2,048-Bit Serial EEPROM(2KB串行EEPROM) PDF資料下載
參數(shù)資料
| 型號： | IS93C56-3 |
| 廠商： | Integrated Silicon Solution, Inc. |
| 英文描述： | 2,048-Bit Serial EEPROM(2KB串行EEPROM) |
| 中文描述： | 2,048位串行EEPROM（2KB的串行EEPROM中） |
| 文件頁數(shù)： | 2/10頁 |
| 文件大?。?/td> | 79K |
| 代理商： | IS93C56-3 |
IS93C56-3
2
Integrated Silicon Solution, Inc.
EE007-1F
09/03/99
ISSI
PIN CONFIGURATION
8-Pin DIP
1
2
3
4
8
7
6
5
CS
SK
D
IN
D
OUT
VCC
NC
NC
GND
PIN CONFIGURATION
8-Pin JEDEC Small Outline “G”
PIN CONFIGURATION
8-Pin JEDEC Small Outline “GR”
1
2
3
4
8
7
6
5
NC
VCC
CS
SK
NC
GND
D
OUT
D
IN
1
2
3
4
8
7
6
5
CS
SK
D
IN
D
OUT
VCC
NC
NC
GND
PIN DESCRIPTIONS
CS
Chip Select
SK
Serial Data Clock
D
IN
Serial Data Input
D
OUT
Serial Data Output
NC
Not Connected
Vcc
Power
GND
Ground
Low Voltage Read
The IS93C56-3 has been designed to ensure that data
read operations are reliable in low voltage environments.
The IS93C56-3 is guaranteed to provide accurate data
during read operations with Vcc as low as 2.7V.
Auto Increment Read Operations
In the interest of memory transfer operation applications,
the IS93C56-3 has been designed to output a continuous
stream of memory content in response to a single read
operation instruction. To utilize this function, the system
asserts a read instruction specifying a start location ad-
dress. Once the 16 bits of the addressed word have been
clocked out, the data in consecutively higher address
locations (the address “000000” is assumed as the ad-
dress of “111111") is output. The address will wrap around
continuously with CS HIGH until the chip select (CS)
control pin is brought LOW. This allows for single instruc-
tion data dumps to be executed with a minimum of firm-
ware overhead.
Write Enable (WEN)
The write enable (WEN) instruction must be executed
before any device programming (WRITE, WRALL, ERASE,
ENDURANCE AND DATA RETENTION
The IS93C56-3 is designed for applications requiring up to
100,000 programming cycles (WRITE, WRALL, ERASE
and ERAL). It provides 10 years of secure data retention,
without power after the execution of 100,000 program-
ming cycles.
DEVICE OPERATION
The IS93C56-3 is controlled by seven 9-bit instructions.
Instructions are clocked in (serially) on the D
IN
pin. Each
instruction begins with a logical “1” (the start bit). This is
followed by the opcode (2 bits), the address field (8 bits),
and data, if appropriate. The clock signal (SK) may be
halted at any time and the IS93C56-3 will remain in its last
state. This allows full static flexibility and maximum power
conservation.
Read (READ)
The READ instruction is the only instruction that outputs
serial data on the D
OUT
pin. After the read instruction and
address have been decoded, data is transferred from the
selected memory register into a 16-bit serial shift register.
(Please note that one logical “0” bit precedes the actual
16-bit output data string.) The output on D
OUT
changes
during the low-to-high transitions of SK (see Figure 3).
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| IS93C56A | 2K-BIT/4K-BIT SERIAL ELECTRICALLY ERASABLE PROM |
| IS93C56A-2GRI | 2K-BIT/4K-BIT SERIAL ELECTRICALLY ERASABLE PROM |
| IS93C56A-2GRLI | 2K-BIT/4K-BIT SERIAL ELECTRICALLY ERASABLE PROM |
| IS93C56A-2PI | 2K-BIT/4K-BIT SERIAL ELECTRICALLY ERASABLE PROM |
| IS93C56A-2PLI | 2K-BIT/4K-BIT SERIAL ELECTRICALLY ERASABLE PROM |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| IS93C56-3G | 制造商:ISSI 制造商全稱:Integrated Silicon Solution, Inc 功能描述:2,048-BIT SERIAL ELECTRICALLY ERASABLE PROM |
| IS93C56-3GI | 制造商:ISSI 制造商全稱:Integrated Silicon Solution, Inc 功能描述:2,048-BIT SERIAL ELECTRICALLY ERASABLE PROM |
| IS93C56-3GR | 制造商:ISSI 制造商全稱:Integrated Silicon Solution, Inc 功能描述:2,048-BIT SERIAL ELECTRICALLY ERASABLE PROM |
| IS93C56-3GRI | 制造商:ISSI 制造商全稱:Integrated Silicon Solution, Inc 功能描述:2,048-BIT SERIAL ELECTRICALLY ERASABLE PROM |
| IS93C56-3P | 制造商:ISSI 制造商全稱:Integrated Silicon Solution, Inc 功能描述:2,048-BIT SERIAL ELECTRICALLY ERASABLE PROM |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。