參數(shù)資料
型號(hào): IS89C51-24PLI
廠商: INTEGRATED SILICON SOLUTION INC
元件分類: 微控制器/微處理器
英文描述: 8-BIT, FLASH, 24 MHz, MICROCONTROLLER, PQCC44
封裝: PLASTIC, LCC-44
文件頁(yè)數(shù): 4/48頁(yè)
文件大?。?/td> 371K
代理商: IS89C51-24PLI
IS89C51
12
1-800-379-4774 — Integrated Silicon Solution, Inc.
MC016-1C
11/21/98
ISSI
IP:
Interrupt Priority Register. Bit Addressable.
7
6
54321
0
PS
PT1
PX1
PT0 PX0
Register Description:
IP.7
Not implemented, reserve for future use(3)
IP.6
Not implemented, reserve for future use(3)
IP.5
Not implemented, reserve for future use(3)
PS
IP.4
Defines Serial Port interrupt priority level
PT1
IP.3
Defines Timer 1 interrupt priority level
PX1
IP.2
Defines External Interrupt 1 priority level
PT0
IP.1
Defines Timer 0 interrupt priority level
PX0
IP.0
Defines External Interrupt 0 priority level
Notes:
1. In order to assign higher priority to an interrupt the
coresponding bit in the IP register must be set to 1. While
an interrupt service is in progress, it cannot be interrupted
by a lower or same level interrupt.
2. Priority within level is only to resolve simultaneous
requests of the same priority level. From high-to-low,
interrupt sources are listed below:
IE0
TF0
IE1
TF1
RI or TI
3. User software should not write 1s to reserved bits. These
bits may be used in future products to invoke new features.
TCON:
Timer/Counter Control Register. Bit Addressable
7
6
54321
0
TF1
TR1
TF0
TR0
IE1
IT1
IE0
IT0
Register Description:
TF1
TCON.7
Timer 1 overflow flag. Set by hardware
when the Timer/Counter 1 overflows.
Cleared by hardware as processor
vectors to the interrupt service routine.
TR1
TCON.6
Timer 1 run control bit. Set/Cleared by
software to turn Timer/Counter 1 ON/
OFF.
TF0
TCON.5
Timer 0 overflow flag. Set by hardware
when the Timer/Counter 0 overflows.
Cleared by hardware as processor
vectors to the interrupt service routine.
TR0
TCON.4
Timer 0 run control bit. Set/Cleared by
software to turn Timer/Counter 0 ON/
OFF.
IE1
TCON.3
External Interrupt 1 edge flag. Set by
hardware when the External Interrupt
edge is detected. Cleared by hardware
when interrupt is processed.
IT1
TCON.2
Interrupt 1 type control bit. Set/Cleared
by software specify falling edge/low level
triggered External Interrupt.
IE0
TCON.1
External Interrupt 0 edge flag. Set by
hardware when the External Interrupt
edge is detected. Cleared by hardware
when interrupt is processed.
IT0
TCON.0
Interrupt 0 type control bit. Set/Cleared
by software specify falling edge/low level
triggered External Interrupt.
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