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參數(shù)資料
| 型號(hào)： | IS82C50A-5Z |
| 廠商： | Intersil |
| 文件頁(yè)數(shù)： | 8/25頁(yè) |
| 文件大小： | 0K |
| 描述： | IC PERIPH UART/BRG 10MHZ 44-PLCC |
| 標(biāo)準(zhǔn)包裝： | 26 |
| 特點(diǎn)： | 單芯片 UART/BRG |
| 通道數(shù)： | 1，UART |
| 規(guī)程： | RS232C |
| 電源電壓： | 4.5 V ~ 5.5 V |
| 帶并行端口： | 是 |
| 帶故障啟動(dòng)位檢測(cè)功能： | 是 |
| 帶調(diào)制解調(diào)器控制功能： | 是 |
| 帶CMOS： | 是 |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 44-LCC（J 形引線） |
| 供應(yīng)商設(shè)備封裝： | 44-PLCC |
| 包裝： | 管件 |
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16
FN2958.5
August 24, 2006
82C50A
Programming
The 82C50A is programmed by the control registers LCR,
lER, DLL and DLM, and MCR. These control words define
the character length, number of stop bits, parity, baud rate,
and modem interface.
While the control registers can be written in any order, the
lER should be written to last because it controls the interrupt
enables. Once the 82C50A is programmed and operational,
these registers can be updated any time the 82C50A is not
transmitting or receiving data.
The control signals required to access 82C50A internal
registers are shown below.
Software Reset
A software reset of the 82C50A is a useful method for
returning to a completely known state without a system
reset. Such a reset consists of writing to the LCR, Divisor
Latches, and MCR registers. The LSR and RBR registers
should be read prior to enabling interrupts in order to clear
out any residual data or status bits which may be invalid for
subsequent operation.
Crystal Operation
The 82C50A crystal oscillator circuitry is designed to operate
with a fundamental mode, parallel resonant crystal. Table 8
shows the required crystal parameters and crystal circuit
configuration, respectively.
When using an external clock source, the XTAL1 input is
driven and the XTAL2 output is left open. Power
consumption when using an external clock is typically 50%
of that required when using a crystal. This is due to the
sinusoidal nature of the drive circuitry when using a crystal.
The maximum frequency of the 82C50A is 10MHz with an
external clock or a crystal attached to XTAL1 and XTAL2.
Using the external clock or crystal, and a divide by one
divisor, the maximum BAUDOUT is 10MHz, and the
maximum data rate is 625Kbps.
TABLE 8. TYPICAL CRYSTAL OSCILLATOR CIRCUIT
PARAMETER
Frequency
1.0 to 10MHz
Type of Operation
Parallel Resonant, Fundamental
Mode
Load Capacitance (CL)
20 or 32pF (Typ)
RSERIES (Max)
100
Ω (f = 10MHz, CL = 32pF)
200
Ω (f = 10MHz, CL = 20pF)
FIGURE 2. TYPICAL CRYSTAL OSCILLATOR CIRCUIT
CL
XTAL
XTAL1
XTAL2
TO
BAUD RATE
GENERATOR
LOGIC
PIN 17
PIN 16
RS
CL
82C50A
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