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參數(shù)資料
| 型號： | IS63LV1024L-12KI |
| 廠商： | INTEGRATED SILICON SOLUTION INC |
| 元件分類： | DRAM |
| 英文描述： | 128K x 8 HIGH-SPEED CMOS STATIC RAM 3.3V REVOLUTIONARY PINOUT |
| 中文描述： | 128K X 8 STANDARD SRAM, 12 ns, PDSO32 |
| 封裝： | 0.400 INCH, PLASTIC, SOJ-32 |
| 文件頁數(shù)： | 7/9頁 |
| 文件大?。?/td> | 45K |
| 代理商： | IS63LV1024L-12KI |
Integrated Silicon Solution, Inc. — www.issi.com —
1-800-379-4774
Rev. B
08/07/02
7
IS63LV1024L
ISSI
WRITE CYCLE SWITCHING CHARACTERISTICS
(1,3)
(Over Operating Range)
-8 ns
-10 ns
Min.
-12 ns
Min.
Symbol
t
WC
t
SCE
t
AW
Parameter
Min.
Max.
Max.
Max.
Unit
Write Cycle Time
8
—
10
—
12
—
ns
CE
to Write End
7
—
7
—
8
—
ns
Address Setup Time to
Write End
8
—
8
—
8
—
ns
t
HA
Address Hold from
Write End
0
—
0
—
0
—
ns
t
SA
t
PWE
1
t
PWE
2
t
SD
t
HD
t
HZWE
(2)
t
LZWE
(2)
Address Setup Time
0
—
0
—
0
—
ns
(1)
WE
Pulse Width (
OE
High)
7
—
7
—
8
—
ns
(2)
WE
Pulse Width (
OE
Low)
8
—
10
—
12
—
ns
Data Setup to Write End
5
—
5
—
6
—
ns
Data Hold from Write End
0
—
0
—
0
—
ns
WE
LOW to High-Z Output
—
4
—
5
—
6
ns
WE
HIGH to Low-Z Output
3
—
3
—
3
—
ns
Notes:
1. Test conditions assume signal transition times of 3ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V and
output loading specified in Figure 1a.
2. Tested with the load in Figure 1b. Transition is measured ±500 mV from steady-state voltage. Not 100% tested.
3. The internal write time is defined by the overlap of
CE
LOW and
WE
LOW. All signals must be in valid states to initiate a Write, but
any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the rising or falling edge of
the signal that terminates the Write.
AC WAVEFORMS
WRITE CYCLE NO. 1
(1,2
(
CE
Controlled,
OE
= HIGH or LOW)
DATA UNDEFINED
t
WC
VALID ADDRESS
t
SCE
t
PWE1
t
PWE2
t
AW
t
HA
HIGH-Z
t
HD
t
SA
t
HZWE
ADDRESS
CE
WE
D
OUT
D
IN
DATA
IN
VALID
t
LZWE
t
SD
CE_WR1.eps
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