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參數(shù)資料
| 型號(hào)： | IS62WV51216BLL |
| 廠商： | Integrated Silicon Solution, Inc. |
| 英文描述： | 512K x 16 LOW VOLTAGE, ULTRA LOW POWER CMOS STATIC RAM |
| 中文描述： | 為512k × 16低電壓，超低功耗的CMOS靜態(tài)RAM |
| 文件頁數(shù)： | 10/16頁 |
| 文件大小： | 137K |
| 代理商： | IS62WV51216BLL |
10
Integrated Silicon Solution, Inc. — www.issi.com —
1-800-379-4774
Rev. B
02/24/05
IS62WV51216ALL, IS62WV51216BLL
ISSI
Notes:
1. WRITE is an internally generated signal asserted during an overlap of the LOW states on the
CS1
, CS2 and
WE
inputs and at
least one of the
LB
and
UB
inputs being in the LOW state.
2. WRITE = (
CS1
) [ (
LB
) = (
UB
) ] (
WE
).
AC WAVEFORMS
WRITE CYCLE NO. 1
(1,2)
(
CS1
Controlled,
OE
= HIGH or LOW)
DATA-IN VALID
DATA UNDEFINED
t
WC
t
SCS1
t
SCS2
t
AW
t
HA
t
PWE
t
HZWE
HIGH-Z
t
LZWE
t
SA
t
SD
t
HD
ADDRESS
CS1
CS2
WE
DOUT
DIN
LB
,
UB
t
PWB
WRITE CYCLE SWITCHING CHARACTERISTICS
(1,2)
(Over Operating Range)
45ns
55 ns
70 ns
Symbol
t
WC
t
SCS1/
t
SCS2
CS1/
CS2 to Write End
t
AW
Address Setup Time to Write End
t
HA
Address Hold from Write End
t
SA
Address Setup Time
t
PWB
LB
,
UB
Valid to End of Write
t
PWE
(4)
WE
Pulse Width
t
SD
Data Setup to Write End
t
HD
Data Hold from Write End
t
HZWE
(3)
WE
LOW to High-Z Output
t
LZWE
(3)
WE
HIGH to Low-Z Output
Parameter
Write Cycle Time
Min.
45
35
35
0
0
35
35
20
0
—
5
Max.
—
—
—
—
—
—
—
—
—
20
—
Min.
55
45
45
0
0
45
40
25
0
—
5
Max.
—
—
—
—
—
—
—
—
—
20
—
Min.
70
60
60
0
0
60
50
30
0
—
5
Max.
—
—
—
—
—
—
—
—
—
30
—
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Notes:
1. Test conditions assume signal transition times of 5 ns or less, timing reference levels of 0.9V/1.5V, input pulse levels of 0.4 to
V
DD
-0.2V/0.4V to V
DD
-0.3V and output loading specified in Figure 1.
2.
The internal write time is defined by the overlap of
CS1
LOW, CS2 HIGH and
UB
or
LB
, and
WE
LOW. All signals must be in valid states to initiate a Write, but
any one can go inactive to
terminate the Write. The Data Input Setup and Hold timing are referenced to the rising or falling edge of the signal that terminates the
write.
3. Tested with the load in Figure 2. Transition is measured ±500 mV from steady-state voltage. Not 100% tested.
4. t
PWE
> t
HZWE
+ t
SD
when
OE
is LOW.
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| IS62WV51216BLL-55BLI | 512K x 16 LOW VOLTAGE, ULTRA LOW POWER CMOS STATIC RAM |
| IS62WV51216BLL-55TI | 512K x 16 LOW VOLTAGE, ULTRA LOW POWER CMOS STATIC RAM |
| IS62WV51216BLL-55TLI | 512K x 16 LOW VOLTAGE, ULTRA LOW POWER CMOS STATIC RAM |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| IS62WV51216BLL-45B | 制造商:ISSI 制造商全稱:Integrated Silicon Solution, Inc 功能描述:512K x 16 LOW VOLTAGE, ULTRA LOW POWER CMOS STATIC RAM |
| IS62WV51216BLL-55BI | 功能描述:靜態(tài)隨機(jī)存取存儲(chǔ)器 8Mb 512Kx16 55ns Async 靜態(tài)隨機(jī)存取存儲(chǔ)器 RoHS:否 制造商:Cypress Semiconductor 存儲(chǔ)容量:16 Mbit 組織:1 M x 16 訪問時(shí)間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
| IS62WV51216BLL-55BI-TR | 功能描述:靜態(tài)隨機(jī)存取存儲(chǔ)器 8Mb 512Kx16 55ns Async 靜態(tài)隨機(jī)存取存儲(chǔ)器 RoHS:否 制造商:Cypress Semiconductor 存儲(chǔ)容量:16 Mbit 組織:1 M x 16 訪問時(shí)間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
| IS62WV51216BLL-55BLI | 功能描述:靜態(tài)隨機(jī)存取存儲(chǔ)器 8Mb 512Kx16 55ns Async 靜態(tài)隨機(jī)存取存儲(chǔ)器 RoHS:否 制造商:Cypress Semiconductor 存儲(chǔ)容量:16 Mbit 組織:1 M x 16 訪問時(shí)間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
| IS62WV51216BLL-55BLI U1137A | 制造商:Integrated Silicon Solution Inc 功能描述: |
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