參數(shù)資料
型號: IS62WV2568BLL-55HLI
廠商: INTEGRATED SILICON SOLUTION INC
元件分類: DRAM
英文描述: 256K x 8 LOW VOLTAGE, ULTRA LOW POWER CMOS STATIC RAM
中文描述: 256K X 8 STANDARD SRAM, 55 ns, PDSO32
封裝: LEAD FREE, PLASTIC, STSOP1-32
文件頁數(shù): 6/14頁
文件大小: 85K
代理商: IS62WV2568BLL-55HLI
6
Integrated Silicon Solution, Inc. — www.issi.com —
1-800-379-4774
Rev. B
06/20/05
IS62WV2568ALL, IS62WV2568BLL
ISSI
AC WAVEFORMS
READ CYCLE NO. 1
(1,2)
(Address Controlled) (
CS1
=
OE
= V
IL
,
CS2 =
WE
= V
IH
)
DATA VALID
PREVIOUS DATA VALID
t
AA
t
OHA
t
OHA
t
RC
D
OUT
ADDRESS
READ CYCLE SWITCHING CHARACTERISTICS
(1)
(Over Operating Range)
55 ns
70 ns
Symbol
t
RC
t
AA
t
OHA
t
ACS1/
t
ACS2
t
DOE
t
HZOE
(2)
t
LZOE
(2)
t
HZCS1/
t
HZCS2
(2)
t
LZCS1/
t
LZCS2
(2)
Parameter
Min.
Max.
Min.
Max.
Unit
Read Cycle Time
55
70
ns
Address Access Time
55
70
ns
Output Hold Time
10
10
ns
CS1/
CS2 Access Time
55
70
ns
OE
Access Time
25
35
ns
OE
to High-Z Output
20
25
ns
OE
to Low-Z Output
5
5
ns
CS1/
CS2 to High-Z Output
0
20
0
25
ns
CS1/
CS2 to Low-Z Output
10
10
ns
Notes:
1. Test conditions assume signal transition times of 5 ns or less, timing reference levels of 0.9V, input pulse levels of 0.4 to 1.4V
and output loading specified in Figure 1.
2. Tested with the load in Figure 2. Transition is measured ±500 mV from steady-state voltage. Not 100% tested.
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