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參數(shù)資料
| 型號： | IS61S6432-7TQ |
| 廠商： | INTEGRATED SILICON SOLUTION INC |
| 元件分類： | DRAM |
| 英文描述： | 64K x 32 SYNCHRONOUS PIPELINE STATIC RAM |
| 中文描述： | 64K X 32 CACHE SRAM, 7 ns, PQFP100 |
| 封裝： | TQFP-100 |
| 文件頁數(shù)： | 7/19頁 |
| 文件大?。?/td> | 140K |
| 代理商： | IS61S6432-7TQ |
Integrated Silicon Solution, Inc.
1-800-379-4774
Rev.
B
06/28/01
7
IS61S6432
ISSI
CAPACITANCE
(1,2)
Symbol
Parameter
Conditions
Max.
Unit
C
IN
Input Capacitance
V
IN
= 0V
6
pF
C
OUT
Input/Output Capacitance
V
OUT
= 0V
8
pF
Notes:
1. Tested initially and after any design or process changes that may affect these parameters.
2. Test conditions: T
A
= 25
°
C, f = 1 MHz, Vcc = 3.3V.
AC TEST CONDITIONS
Parameter
Input Pulse Level
Input Rise and Fall Times
Input and Output Timing
and Reference Level
Output Load
Unit
0V to 3.0V
1.5 ns
1.5V
See Figures 1 and 2
Figure 1
Output
Buffer
Z
O
= 50
1.5V
50
30 pF
317
5 pF
Including
jig and
scope
351
OUTPUT
3.3V
Figure 2
AC TEST LOADS
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