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參數(shù)資料
| 型號： | IS61S6432-7PQ |
| 廠商： | INTEGRATED SILICON SOLUTION INC |
| 元件分類： | DRAM |
| 英文描述： | Octal D-Type Transparent Latches With 3-State Outputs 20-SOIC -40 to 85 |
| 中文描述： | 64K X 32 CACHE SRAM, 7 ns, PQFP100 |
| 封裝： | PLASTIC, QFP-100 |
| 文件頁數(shù)： | 16/19頁 |
| 文件大小： | 140K |
| 代理商： | IS61S6432-7PQ |
PB
Integrated Silicon Solution, Inc.
1-800-379-4774
Rev.
B
06/28/01
IS61S6432
ISSI
SNOOZE AND RECOVERY CYCLE SWITCHING CHARACTERISTICS
(1)
(Over Operating Range)
-200
(2)
Min. Max.
-166
-133
-117
Symbol
Parameter
Min.
Max
Min. Max.
Min. Max.
Unit
t
KC
Cycle Time
5
—
6
—
7.5
—
8.5
—
ns
t
KH
Clock High Time
1.6
—
2.4
—
2.8
—
3
—
ns
t
KL
Clock Low Time
1.6
—
2.4
—
2.8
—
3
—
ns
t
KQ
Clock Access Time
—
4
—
5
—
5
—
5
ns
t
KQX
(3)
Clock High to Output Invalid
1
—
1.5
—
1.5
—
1.5
—
ns
t
KQLZ
(3,4)
Clock High to Output Low-Z
0
—
0
—
0
—
0
—
ns
t
KQHZ
(3,4)
Clock High to Output High-Z
1
3.5
1.5
5
1.5
5
1.5
6
ns
t
OEQ
Output Enable to Output Valid
—
3.5
—
5
—
5
—
5
ns
t
OEQX
(3)
Output Disable to Output Invalid
0
—
0
—
0
—
0
—
ns
t
OELZ
(3,4)
Output Enable to Output Low-Z
0
—
0
—
0
—
0
—
ns
t
OEHZ
(3,4)
Output Disable to Output High-Z
—
3
—
3
—
3
—
4
ns
t
AS
Address Setup Time
2
—
2.5
—
2.5
—
2.5
—
ns
t
SS
Address Status Setup Time
2
—
2.5
—
2.5
—
2.5
—
ns
t
CES
Chip Enable Setup Time
2
—
2.5
—
2.5
—
2.5
—
ns
t
AH
Address Hold Time
2
—
2.5
—
2.5
—
2.5
—
ns
t
SH
Address Status Hold Time
2
—
2.5
—
2.5
—
2.5
—
ns
t
CEH
Chip Enable Hold Time
2
—
2.5
—
2.5
—
2.5
—
ns
t
ZZS
(5)
ZZ Standby
—
8
2
—
2
—
2
—
cyc
t
ZZREC
(6)
ZZ Recovery
8
—
2
—
2
—
2
—
cyc
Notes:
1. Configuration signal MODE is static and must not change during normal operation.
2.
ADVANCE INFORMATION ONLY.
3. Guaranteed but not 100% tested. This parameter is periodically sampled.
4. Tested with load in Figure 2.
5. The assertion of ZZ allows the SRAM to enter a lower power state than when deselected within the time specified. Data
retention is guaranteed when ZZ is asserted and clock remains active.
6. ADSC and ADSP must not be asserted for at least two cycles after leaving ZZ state.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| IS61S6432-7PQI | Octal D-Type Transparent Latches With 3-State Outputs 20-SOIC -40 to 85 |
| IS61S6432-7TQ | 64K x 32 SYNCHRONOUS PIPELINE STATIC RAM |
| IS61S6432-7TQI | Octal D-Type Transparent Latches With 3-State Outputs 20-SOIC -40 to 85 |
| IS61S6432-8PQ | Octal D-Type Transparent Latches With 3-State Outputs 20-SOIC -40 to 85 |
| IS61S6432-8TQ | 64K x 32 SYNCHRONOUS PIPELINE STATIC RAM |
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