參數(shù)資料
型號(hào)： IS61S6432-200TQ
廠商： INTEGRATED SILICON SOLUTION INC
元件分類： DRAM
英文描述： Quadruple 2-Input Positive-OR Gates 14-TSSOP -40 to 85
中文描述： 64K X 32 CACHE SRAM, 4 ns, PQFP100
封裝： TQFP-100
文件頁數(shù)： 11/19頁
文件大小： 140K
代理商： IS61S6432-200TQ
Integrated Silicon Solution, Inc.
1-800-379-4774
Rev.
B
06/28/01
11
IS61S6432
ISSI
WRITE CYCLE SWITCHING CHARACTERISTICS
(Over Operating Range)
-200
(1)
Min. Max.
-166
-133
-117
Symbol
Parameter
Min. Max.
Min. Max.
Min. Max.
Unit
t
KC
Cycle Time
5
—
6
—
7.5
—
8.5
—
ns
t
KH
Clock High Time
1.6
—
2.4
—
2.8
—
3
—
ns
t
KL
Clock Low Time
1.6
—
2.4
—
2.8
—
3
—
ns
t
AS
Address Setup Time
2
—
2.5
—
2.5
—
2.5
—
ns
t
SS
Address Status Setup Time
2
—
2.5
—
2.5
—
2.5
—
ns
t
WS
Write Setup Time
2
—
2.5
—
2.5
—
2.5
—
ns
t
DS
Data In Setup Time
2
—
2.5
—
2.5
—
2.5
—
ns
t
CES
Chip Enable Setup Time
2
—
2.5
—
2.5
—
2.5
—
ns
t
AVS
Address Advance Setup Time
2
—
2.5
—
2.5
—
2.5
—
ns
t
AH
Address Hold Time
0.5
—
0.5
—
0.5
—
0.5
—
ns
t
SH
Address Status Hold Time
0.5
—
0.5
—
0.5
—
0.5
—
ns
t
DH
Data In Hold Time
0.5
—
0.5
—
0.5
—
0.5
—
ns
t
WH
Write Hold Time
0.5
—
0.5
—
0.5
—
0.5
—
ns
t
CEH
Chip Enable Hold Time
0.5
—
0.5
—
0.5
—
0.5
—
ns
t
AVH
Address Advance Hold Time
0.5
—
0.5
—
0.5
—
0.5
—
ns
t
CFG
(2)
Configuration Setup
25
—
25
—
30
—
35
—
ns
-5
-6
-7
-8
Symbol
Parameter
Min. Max.
Min. Max.
Min. Max.
Min. Max.
Unit
t
KC
Cycle Time
10
—
12
—
13
—
15
—
ns
t
KH
Clock High Time
3.5
—
4
—
6
—
6
—
ns
t
KL
Clock Low Time
3.5
—
4
—
6
—
6
—
ns
t
AS
Address Setup Time
2.5
—
2.5
—
2.5
—
2.5
—
ns
t
SS
Address Status Setup Time
2.5
—
2.5
—
2.5
—
2.5
—
ns
t
WS
Write Setup Time
2.5
—
2.5
—
2.5
—
2.5
—
ns
t
DS
Data In Setup Time
2.5
—
2.5
—
2.5
—
2.5
—
ns
t
CES
Chip Enable Setup Time
2.5
—
2.5
—
2.5
—
2.5
—
ns
t
AVS
Address Advance Setup Time
2.5
—
2.5
—
2.5
—
2.5
—
ns
t
AH
Address Hold Time
0.5
—
0.5
—
0.5
—
0.5
—
ns
t
SH
Address Status Hold Time
0.5
—
0.5
—
0.5
—
0.5
—
ns
t
DH
Data In Hold Time
0.5
—
0.5
—
0.5
—
0.5
—
ns
t
WH
Write Hold Time
0.5
—
0.5
—
0.5
—
0.5
—
ns
t
CEH
Chip Enable Hold Time
0.5
—
0.5
—
0.5
—
0.5
—
ns
t
AVH
Address Advance Hold Time
0.5
—
0.5
—
0.5
—
0.5
—
ns
t
CFG
(2)
Configuration Setup
35
—
45
—
52
—
60
—
ns
Note:
1.
ADVANCE INFORMATION ONLY.
2. Configuration signal MODE is static and must not change during normal operation.
相關(guān)PDF資料
PDF描述
IS61S6432-5PQ Quadruple 2-Input Positive-OR Gates 14-TSSOP -40 to 85
IS61S6432-5PQI 64K x 32 SYNCHRONOUS PIPELINE STATIC RAM
IS61S6432-5TQ 64K x 32 SYNCHRONOUS PIPELINE STATIC RAM
IS61S6432-5TQI 64K x 32 SYNCHRONOUS PIPELINE STATIC RAM
IS61S6432-6PQ 64K x 32 SYNCHRONOUS PIPELINE STATIC RAM
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