參數(shù)資料
型號(hào): IS61NVP204818-166TQ
廠商: INTEGRATED SILICON SOLUTION INC
元件分類(lèi): SRAM
英文描述: 2M X 18 ZBT SRAM, 3.5 ns, PQFP100
封裝: TQFP-100
文件頁(yè)數(shù): 20/22頁(yè)
文件大?。?/td> 221K
代理商: IS61NVP204818-166TQ
Integrated Silicon Solution, Inc. — www.issi.com
7
Rev. 00A
05/02/07
IS61NLP102436/IS61NVP102436
IS61NLP204818/IS61NVP204818
ASYNCHRONOUS TRUTH TABLE(1)
Operation
ZZ
OE
I/O STATUS
Sleep Mode
H
X
High-Z
Read
LL
DQ
L
H
High-Z
Write
L
X
Din, High-Z
Deselected
L
X
High-Z
Notes:
1. X means "Don't Care".
2. For write cycles following read cycles, the output buffers must be disabled with
OE, otherwise data bus
contention will occur.
3. Sleep Mode means power Sleep Mode where stand-by current does not depend on cycle time.
4. Deselected means power Sleep Mode where stand-by current depends on cycle time.
WRITE TRUTH TABLE (x18)
Operation
WE
BW
BWa
BW
BWb
READ
H
X
WRITE BYTE a
L
H
WRITE BYTE b
L
H
L
WRITE ALL BYTEs
L
WRITE ABORT/NOP
L
H
Notes:
1. X means "Don't Care".
2. All inputs in this table must beet setup and hold time around the rising edge of CLK.
WRITE TRUTH TABLE (x36)
Operation
WE
BW
BWa
BW
BWb
BW
BWc
BW
BWd
READ
H
X
WRITE BYTE a
L
H
WRITE BYTE b
L
H
L
H
WRITE BYTE c
L
H
L
H
WRITE BYTE d
L
H
L
WRITE ALL BYTEs
L
WRITE ABORT/NOP
L
H
Notes:
1. X means "Don't Care".
2. All inputs in this table must beet setup and hold time around the rising edge of CLK.
INTERLEAVED BURST ADDRESS TABLE (MODE = VDD or NC)
External Address
1st Burst Address
2nd Burst Address
3rd Burst Address
A1 A0
00
01
10
11
01
00
11
10
11
00
01
11
10
01
00
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