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| 型號(hào)： | IS61NP12832-150B |
| 廠商： | INTEGRATED SILICON SOLUTION INC |
| 元件分類(lèi)： | DRAM |
| 英文描述： | PIPELINE NO WAIT STATE BUS SRAM |
| 中文描述： | 128K X 32 ZBT SRAM, 3.8 ns, PBGA119 |
| 封裝： | PLASTIC, BGA-119 |
| 文件頁(yè)數(shù)： | 12/20頁(yè) |
| 文件大小： | 154K |
| 代理商： | IS61NP12832-150B |
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12
Integrated Silicon Solution, Inc.
—
1-800-379-4774
PRELIMINARY INFORMATION
Rev. 00C
11/30/00
IS61NP12832
IS61NLP12832
IS61NP12836
IS61NLP12836
IS61NP25618
IS61NLP25618
ISSI
READ/WRITE CYCLE SWITCHING CHARACTERISTICS
(1)
(Over Operating Range)
-150*
Min. Max.
-133
-100
Min. Max.
Symbol
Parameter
Min. Max.
Unit
fmax
Clock Frequency
—
150
—
133
—
100
MHz
t
KC
Cycle Time
6.7
—
7.5
—
10
—
ns
t
KH
Clock High Time
2.5
—
3
—
3
—
ns
t
KL
Clock Low Time
2.5
—
3
—
3
—
ns
t
KQ
Clock Access Time
—
3.8
—
4.2
—
5
ns
t
KQX
(2)
Clock High to Output Invalid
1.5
—
1.5
—
1.5
—
ns
t
KQLZ
(2,3)
Clock High to Output Low-Z
0
—
0
—
0
—
ns
t
KQHZ
(2,3)
Clock High to Output High-Z
—
3
—
3.5
—
3.5
ns
t
OEQ
Output Enable to Output Valid
—
3.8
—
4.2
—
5
ns
t
OELZ
(2,3)
Output Enable to Output Low-Z
0
—
0
—
0
—
ns
t
OEHZ
(2,3)
Output Disable to Output High-Z
—
3.5
—
3.5
—
3.5
ns
t
AS
Address Setup Time
1.5
—
1.5
—
1.5
—
ns
t
WS
Read/Write Setup Time
1.5
—
1.5
—
1.5
—
ns
t
CES
Chip Enable Setup Time
1.5
—
1.5
—
1.5
—
ns
t
SE
Clock Enable Setup Time
1.5
—
1.5
—
1.5
—
ns
t
AVS
Address Advance Setup Time
1.5
—
1.5
—
1.5
—
ns
t
DS
Data Setup Time
2.0
—
2.0
—
2.0
—
ns
t
AH
Address Hold Time
0.5
—
0.5
—
0.5
—
ns
t
HE
Clock EnableHold Time
0.5
—
0.5
—
0.5
—
ns
t
WH
Write Hold Time
0.5
—
0.5
—
0.5
—
ns
t
CEH
Chip Enable Hold Time
0.5
—
0.5
—
0.5
—
ns
t
ADVH
Address Advance Hold Time
0.5
—
0.5
—
0.5
—
ns
t
DH
Data Hold Time
0.5
—
0.5
—
0.5
—
ns
t
PDS
ZZ High to Power Down
—
2
—
2
—
2
cyc
t
PUS
ZZ Low to Power Down
—
2
—
2
—
2
cyc
*This speed available only in NP version
Notes:
1. Configuration signal MODE is static and must not change during normal operation.
2. Guaranteed but not 100% tested. This parameter is periodically sampled.
3. Tested with load in Figure 2.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| IS61NP12832-150TQ | PIPELINE NO WAIT STATE BUS SRAM |
| IS61NP12832-5B | PIPELINE NO WAIT STATE BUS SRAM |
| IS61NP12832-5TQ | PIPELINE NO WAIT STATE BUS SRAM |
| IS61NP12836 | PIPELINE NO WAIT STATE BUS SRAM |
| IS61NP12836-133B | PIPELINE NO WAIT STATE BUS SRAM |
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| IS61NVF102418-6.5B3 | 功能描述:靜態(tài)隨機(jī)存取存儲(chǔ)器 18Mb,"No-Wait"/Flowthrough,Sync,1Mb x 18,6.5ns,2.5v - I/O,165 Ball BGA RoHS:否 制造商:Cypress Semiconductor 存儲(chǔ)容量:16 Mbit 組織:1 M x 16 訪問(wèn)時(shí)間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
| IS61NVF102418-6.5B3I | 功能描述:靜態(tài)隨機(jī)存取存儲(chǔ)器 18Mb,"No-Wait"/Flowthrough,Sync,1Mb x 18,6.5ns,2.5v - I/O,165 Ball BGA RoHS:否 制造商:Cypress Semiconductor 存儲(chǔ)容量:16 Mbit 組織:1 M x 16 訪問(wèn)時(shí)間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
| IS61NVF102418-6.5B3I-TR | 功能描述:靜態(tài)隨機(jī)存取存儲(chǔ)器 18Mb,"No-Wait"/Flowthrough,Sync,1Mb x 18,6.5ns,2.5v - I/O,165 Ball BGA RoHS:否 制造商:Cypress Semiconductor 存儲(chǔ)容量:16 Mbit 組織:1 M x 16 訪問(wèn)時(shí)間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
| IS61NVF102418-6.5B3-TR | 功能描述:靜態(tài)隨機(jī)存取存儲(chǔ)器 18Mb,"No-Wait"/Flowthrough,Sync,1Mb x 18,6.5ns,2.5v - I/O,165 Ball BGA RoHS:否 制造商:Cypress Semiconductor 存儲(chǔ)容量:16 Mbit 組織:1 M x 16 訪問(wèn)時(shí)間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
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