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參數(shù)資料
| 型號： | IS61NP12832-133B |
| 廠商： | INTEGRATED SILICON SOLUTION INC |
| 元件分類： | DRAM |
| 英文描述： | PIPELINE NO WAIT STATE BUS SRAM |
| 中文描述： | 128K X 32 ZBT SRAM, 4.2 ns, PBGA119 |
| 封裝： | PLASTIC, BGA-119 |
| 文件頁數(shù)： | 6/20頁 |
| 文件大?。?/td> | 154K |
| 代理商： | IS61NP12832-133B |
6
Integrated Silicon Solution, Inc.
—
1-800-379-4774
PRELIMINARY INFORMATION
Rev. 00C
11/30/00
IS61NP12832
IS61NLP12832
IS61NP12836
IS61NLP12836
IS61NP25618
IS61NLP25618
ISSI
SYNCHRONOUS TRUTH TABLE
(1)
Address
Used
Operation
CS
1
CS2
CS
2
ADV
WE
BW
x
OE
CKE
CLK
Not Selected Continue
Begin Burst Read
Continue Burst Read
NOP/Dummy Read
Dummy Read
Begin Burst Write
Continue Burst Write
NOP/Write Abort
Write Abort
Ignore Clock
N/A
X
L
X
L
X
L
X
L
X
X
X
H
X
H
X
H
X
H
X
X
X
L
X
L
X
L
X
L
X
X
H
L
H
L
H
L
H
L
H
X
X
H
X
H
X
L
X
L
X
X
X
X
X
X
X
L
L
H
H
X
X
L
L
H
H
X
X
X
X
X
L
L
L
L
L
L
L
L
L
H
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
External Address
Next Address
External Address
Next Address
External Address
Next Address
N/A
Next Address
Current Address
Notes:
1. "X" means don't care.
2. The rising edge of clock is symbolized by
↑
3. A continue deselect cycle can only be entered if a deselect cycle is executed first.
4.
WE
= L means Write operation in Write Truth Table.
WE
= H means Read operation in Write Truth Table.
5. Operation finally depends on status of asynchronous pins (ZZ and
OE
).
BURST
READ
DESELECT
BURST
WRITE
BEGIN
READ
BEGIN
WRITE
READ
WRITE
READ
WRITE
BURST
BURST
BURST
DS
DS
DS
READ
DS
DS
READ
WRITE
WRITE
BURST
BURST
WRITE
READ
STATE DIAGRAM
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| IS61NP12832-150B | PIPELINE NO WAIT STATE BUS SRAM |
| IS61NP12832-150TQ | PIPELINE NO WAIT STATE BUS SRAM |
| IS61NP12832-5B | PIPELINE NO WAIT STATE BUS SRAM |
| IS61NP12832-5TQ | PIPELINE NO WAIT STATE BUS SRAM |
| IS61NP12836 | PIPELINE NO WAIT STATE BUS SRAM |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| IS61NP12832-133TQ | 制造商:Integrated Silicon Solution Inc 功能描述: |
| IS61NP12832-133TQ-TR | 制造商:Integrated Silicon Solution Inc 功能描述:SRAM Chip Sync Quad 3.3V 4M-Bit 128K x 32 4.2ns 100-Pin TQFP T/R |
| IS61NP51218-100TQ | 制造商:Integrated Silicon Solution Inc 功能描述: |
| IS61NVF102418-6.5B3 | 功能描述:靜態(tài)隨機(jī)存取存儲器 18Mb,"No-Wait"/Flowthrough,Sync,1Mb x 18,6.5ns,2.5v - I/O,165 Ball BGA RoHS:否 制造商:Cypress Semiconductor 存儲容量:16 Mbit 組織:1 M x 16 訪問時間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
| IS61NVF102418-6.5B3I | 功能描述:靜態(tài)隨機(jī)存取存儲器 18Mb,"No-Wait"/Flowthrough,Sync,1Mb x 18,6.5ns,2.5v - I/O,165 Ball BGA RoHS:否 制造商:Cypress Semiconductor 存儲容量:16 Mbit 組織:1 M x 16 訪問時間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
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