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參數(shù)資料
| 型號： | IS61LV2568-8TI |
| 廠商： | INTEGRATED SILICON SOLUTION INC |
| 元件分類： | DRAM |
| 英文描述： | x8 SRAM |
| 中文描述： | 256K X 8 STANDARD SRAM, 8 ns, PDSO44 |
| 封裝： | TSOP2-44 |
| 文件頁數(shù)： | 4/8頁 |
| 文件大?。?/td> | 88K |
| 代理商： | IS61LV2568-8TI |
IS61LV2568
ISSI
4
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. A
12/19/00
AC TEST LOADS
AC TEST CONDITIONS
Parameter
Input Pulse Level
Input Rise and Fall Times
Input and Output Timing
and Reference Levels
Output Load
Unit
0V to 3.0V
3 ns
1.5V
See Figures 1 and 2
READ CYCLE SWITCHING CHARACTERISTICS
(1)
(Over Operating Range)
- 8 ns
-10 ns
-12 ns
-15 ns
Symbol
Parameter
Min.
Max
Min.
Max.
Min.
Max.
Min.
Max.
Unit
t
RC
Read Cycle Time
8
—
10
—
12
—
15
—
ns
t
AA
Address Access Time
—
8
—
10
—
12
—
15
ns
t
OHA
Output Hold Time
3
—
3
—
3
—
3
—
ns
t
ACE
CE
Access Time
—
8
—
10
—
12
—
15
ns
t
DOE
OE
Access Time
—
3
—
4
—
5
—
6
ns
t
LZOE
(2)
OE
to Low-Z Output
0
—
0
—
0
—
0
—
ns
t
HZOE
(2)
OE
to High-Z Output
0
3
0
4
0
5
0
6
ns
t
LZCE
(2)
CE
to Low-Z Output
3
—
3
—
3
—
3
—
ns
t
HZCE
(2)
CE
to High-Z Output
0
3
0
4
0
5
0
6
ns
Notes:
1. Test conditions assume signal transition times of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V and
output loading specified in Figure 1.
2. Tested with the load in Figure 2. Transition is measured ±200 mV from steady-state voltage. Not 100% tested.
Figure 1
Figure 2
319
30 pF
Including
jig and
scope
353
OUTPUT
3.3V
319
5 pF
Including
jig and
scope
353
OUTPUT
3.3V
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| IS61LV2568J | 制造商:Integrated Silicon Solution Inc 功能描述: |
| IS61LV256-8J | 制造商:ICSI 制造商全稱:Integrated Circuit Solution Inc 功能描述:32K X 8 LOW VOLTAGE CMOS STATIC RAM |
| IS61LV256-8JI | 制造商:ICSI 制造商全稱:Integrated Circuit Solution Inc 功能描述:32K X 8 LOW VOLTAGE CMOS STATIC RAM |
| IS61LV2568L | 制造商:ISSI 制造商全稱:Integrated Silicon Solution, Inc 功能描述:256K x 8 HIGH-SPEED CMOS STATIC RAM |
| IS61LV2568L_08 | 制造商:ISSI 制造商全稱:Integrated Silicon Solution, Inc 功能描述:256K x 8 HIGH-SPEED CMOS STATIC RAM |
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