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參數(shù)資料
| 型號： | IS61LV2568-8KI |
| 廠商： | INTEGRATED SILICON SOLUTION INC |
| 元件分類： | DRAM |
| 英文描述： | x8 SRAM |
| 中文描述： | 256K X 8 STANDARD SRAM, 8 ns, PDSO36 |
| 封裝： | 0.400 INCH, PLASTIC, SOJ-36 |
| 文件頁數(shù)： | 6/8頁 |
| 文件大小： | 88K |
| 代理商： | IS61LV2568-8KI |
IS61LV2568
ISSI
6
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. A
12/19/00
WRITE CYCLE SWITCHING CHARACTERISTICS
(1,2)
(Over Operating Range)
- 8 ns
-10 ns
-12 ns
-15 ns
Symbol
Parameter
Min.
Max
Min.
Max.
Min.
Max.
Min.
Max.
Unit
t
WC
Write Cycle Time
8
—
10
—
12
—
15
—
ns
t
SCE
CE
to Write End
6.5
—
8
—
9
—
10
—
ns
t
AW
Address Setup Time to
Write End
6.5
—
8
—
9
—
10
—
ns
t
HA
Address Hold from
Write End
0
—
0
—
0
—
0
—
ns
t
SA
Address Setup Time
0
—
0
—
0
—
0
—
ns
t
PWE
1
WE
Pulse Width (
OE
= HIGH)
5
—
7
—
8
—
10
—
ns
t
PWE
2
WE
Pulse Width (
OE
= LOW)
6.5
—
8
—
10
—
11
—
ns
t
SD
Data Setup to Write End
4
—
5
—
6
—
7
—
ns
t
HD
Data Hold from Write End
0
—
0
—
0
—
0
—
ns
t
HZWE
(3)
WE
LOW to High-Z Output
—
3
—
4
—
5
—
6
ns
t
LZWE
(3)
WE
HIGH to Low-Z Output
0
—
0
—
0
—
0
—
ns
Notes:
1. Test conditions assume signal transition times of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V and
output loading specified in Figure 1.
2. The internal write time is defined by the overlap of
CE
LOW and
WE
LOW. All signals must be in valid states to initiate a Write,
but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the rising or falling
edge of the signal that terminates the Write.
3. Tested with the load in Figure 2. Transition is measured ±500 mV from steady-state voltage. Not 100% tested.
AC WAVEFORMS
WRITE CYCLE NO. 1
(1,2)
(
CE
Controlled,
OE
= HIGH or LOW)
DATA UNDEFINED
t
WC
VALID ADDRESS
t
SCE
t
PWE1
t
PWE2
t
AW
t
HA
HIGH-Z
t
HD
t
SA
t
HZWE
ADDRESS
CE
WE
D
OUT
D
IN
DATA
IN
VALID
t
LZWE
t
SD
CE_WR1.eps
Note:
1. The internal Write time is defined by the overlap of
CE
= LOW and
WE
= LOW. All signals must be in valid states to initiate a Write, but any
can be deasserted to terminate the Write. The Data Input Setup and Hold timing is referenced to the rising or falling edge of the signal that
terminates the Write.
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PDF描述 |
|---|---|
| IS61LV2568-8TI | x8 SRAM |
| IS61LV256AL-10TLI | 32K x 8 LOW VOLTAGE CMOS STATIC RAM |
| IS61LV256AL-10TI | 32K x 8 LOW VOLTAGE CMOS STATIC RAM |
| IS61LV256AL-10TL | 32K x 8 LOW VOLTAGE CMOS STATIC RAM |
| IS61LV256AL | 32K x 8 LOW VOLTAGE CMOS STATIC RAM |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| IS61LV2568-8T | 制造商:ISSI 制造商全稱:Integrated Silicon Solution, Inc 功能描述:256K x 8 HIGH-SPEED CMOS STATIC RAM |
| IS61LV2568-8TI | 制造商:ISSI 制造商全稱:Integrated Silicon Solution, Inc 功能描述:x8 SRAM |
| IS61LV2568J | 制造商:Integrated Silicon Solution Inc 功能描述: |
| IS61LV256-8J | 制造商:ICSI 制造商全稱:Integrated Circuit Solution Inc 功能描述:32K X 8 LOW VOLTAGE CMOS STATIC RAM |
| IS61LV256-8JI | 制造商:ICSI 制造商全稱:Integrated Circuit Solution Inc 功能描述:32K X 8 LOW VOLTAGE CMOS STATIC RAM |
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