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參數(shù)資料
| 型號(hào)： | IS61LV2568-12TI |
| 廠商： | INTEGRATED SILICON SOLUTION INC |
| 元件分類(lèi)： | DRAM |
| 英文描述： | x8 SRAM |
| 中文描述： | 256K X 8 STANDARD SRAM, 12 ns, PDSO44 |
| 封裝： | TSOP2-44 |
| 文件頁(yè)數(shù)： | 7/8頁(yè) |
| 文件大?。?/td> | 88K |
| 代理商： | IS61LV2568-12TI |
IS61LV2568
ISSI
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. A
12/19/00
7
WRITE CYCLE NO. 2
(1)
(
WE
Controlled,
OE
= HIGH during Write Cycle)
Note:
1. The internal Write time is defined by the overlap of
CE
= LOW and
WE
= LOW. All signals must be in valid states to initiate a Write, but any
can be deasserted to terminate the Write. The Data Input Setup and Hold timing is referenced to the rising or falling edge of the signal that
terminates the Write.
DATA UNDEFINED
LOW
t
WC
VALID ADDRESS
t
PWE1
t
AW
t
HA
HIGH-Z
t
HD
t
SA
t
HZWE
ADDRESS
CE
WE
D
OUT
D
IN
OE
DATA
IN
VALID
t
LZWE
t
SD
CE_WR2.eps
AC WAVEFORMS
WRITE CYCLE NO. 3
(
WE
Controlled:
OE
is LOW During Write Cycle)
Note:
1. The internal Write time is defined by the overlap of
CE
= LOW and
WE
= LOW. All signals must be in valid states to initiate a Write, but any
can be deasserted to terminate the Write. The Data Input Setup and Hold timing is referenced to the rising or falling edge of the signal that
terminates the Write.
DATA UNDEFINED
t
WC
VALID ADDRESS
LOW
LOW
t
PWE2
t
AW
t
HA
HIGH-Z
t
HD
t
SA
t
HZWE
ADDRESS
CE
WE
D
OUT
D
IN
OE
DATA
IN
VALID
t
LZWE
t
SD
CE_WR3.eps
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| IS61LV2568-15K | 制造商:ISSI 制造商全稱:Integrated Silicon Solution, Inc 功能描述:256K x 8 HIGH-SPEED CMOS STATIC RAM |
| IS61LV2568-15KI | 制造商:ISSI 制造商全稱:Integrated Silicon Solution, Inc 功能描述:x8 SRAM |
| IS61LV2568-15T | 制造商:ISSI 制造商全稱:Integrated Silicon Solution, Inc 功能描述:256K x 8 HIGH-SPEED CMOS STATIC RAM |
| IS61LV2568-15TI | 制造商:ISSI 制造商全稱:Integrated Silicon Solution, Inc 功能描述:x8 SRAM |
| IS61LV2568-8K | 制造商:ISSI 制造商全稱:Integrated Silicon Solution, Inc 功能描述:256K x 8 HIGH-SPEED CMOS STATIC RAM |
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