參數(shù)資料
型號(hào): IS61LV12824-8TQ
廠商: INTEGRATED SILICON SOLUTION INC
元件分類: DRAM
英文描述: 128K x 24 HIGH-SPEED CMOS STATIC RAM WITH 3.3V SUPPLY
中文描述: 128K X 24 STANDARD SRAM, 8 ns, PQFP100
封裝: TQFP-100
文件頁數(shù): 8/13頁
文件大?。?/td> 77K
代理商: IS61LV12824-8TQ
IS61LV12824
ISSI
8
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. D
06/22/05
WRITE CYCLE SWITCHING CHARACTERISTICS
(1,3)
(Over Operating Range)
-8
-10
Symbol
t
WC
t
SCE
t
SCE
2
t
AW
Parameter
Min.
Max.
Min.
Max.
Unit
Write Cycle Time
8
10
ns
CE1
,
CE2
to Write End
CE2 to Write End
7
7
8
8
ns
Address Setup Time
to Write End
7
8
ns
t
HA
t
SA
t
PWE
1
t
PWE
2
t
SD
t
HD
t
HZWE
(2)
t
LZWE
(2)
Address Hold from Write End
0
0
ns
Address Setup Time
0
0
ns
WE
Pulse Width (
OE
= HIGH)
6
8
ns
WE
Pulse Width (
OE
= LOW)
6
9
ns
Data Setup to Write End
4.5
5
ns
Data Hold from Write End
0
0
ns
WE
LOW to High-Z Output
3.5
3.5
ns
WE
HIGH to Low-Z Output
3
3
ns
Notes:
1. Test conditions assume signal transition times of 2 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V
and output loading specified in Figure 1.
2. Tested with the load in Figure 2. Transition is measured ±200 mV from steady-state voltage. Not 100% tested.
3. The internal write time is defined by the overlap of
CE1
,
CE2
LOW, CE2 HIGH and
WE
LOW. All signals must be in valid
states to initiate a Write, but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are
referenced to the rising or falling edge of the signal that terminates the write.
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
IS61LV12824-8TQL 制造商:Integrated Silicon Solution Inc 功能描述:
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IS61LV12824-9B 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x24 SRAM
IS61LV12824-9BI 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x24 SRAM
IS61LV12824-9TQ 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x24 SRAM