參數(shù)資料
型號(hào)： IS61DDB22M18-250M3
廠(chǎng)商： INTEGRATED SILICON SOLUTION INC
元件分類(lèi)： DRAM
英文描述： 36 Mb (1M x 36 & 2M x 18) DDR-II (Burst of 2) CIO Synchronous SRAMs
中文描述： 2M X 18 DDR SRAM, 0.35 ns, PBGA165
封裝： 15 X 17 MM, 1 MM PITCH, FBGA-165
文件頁(yè)數(shù)： 1/25頁(yè)
文件大小： 421K
代理商： IS61DDB22M18-250M3
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. B
2/22/05
1
ISSI
36 Mb (1M x 36 & 2M x 18)
DDR-II (Burst of 2) CIO Synchronous SRAMs
Features
1M x 36 or 2M x 18.
On-chip delay-locked loop (DLL) for wide data
valid window.
Common data input/output bus.
Synchronous pipeline read with self-timed late
write operation.
Double data rate (DDR
-II
) interface for read and
write input ports.
Fixed 2-bit burst for read and write operations.
Clock stop support.
Two input clocks (K and K) for address and con-
trol registering at rising edges only.
Two input clocks (C and C) for data output con-
trol.
Two echo clocks (CQ and CQ) that are delivered
simultaneously with data.
+1.8V core power supply and 1.5, 1.8V V
DDQ
,
used with 0.75, 0.9V V
REF
.
HSTL input and output levels.
Registered addresses, write and read controls,
byte writes, data in, and data outputs.
Full data coherency.
Boundary scan using limited set of JTAG 1149.1
functions.
Byte write capability.
Fine ball grid array (FBGA) package
- 15mm x 17mm body size
- 1mm pitch
- 165-ball (11 x 15) array
Programmable impedance output drivers via 5x
user-supplied precision resistor.
Description
The 36Mb
IS61DDB21M36
and
IS61DDB22M18
are synchronous, high-perfor-
mance CMOS static random access memory
(SRAM) devices. These SRAMs have a common I/O
bus. The rising edge of K clock initiates the
read/write operation, and all internal operations are
self-timed.
Refer to the
Timing Reference Diagram for Truth
Table
on page
8
for a description of the basic opera-
tions of these
DDR-II (Burst of 2) CIO
SRAMs.
The input addresses are registered on all rising
edges of the K clock. The DQ bus operates at
double data rate for reads and writes. The following
are registered internally on the rising edge of the K
clock:
Read and write addresses
Address load
Read/write enable
Byte writes
Data-in
The following are registered on the rising edge of
the K clock:
Byte writes
Data-in for second burst addresses
Byte writes can change with the corresponding data-
in to enable or disable writes on a per-byte basis. An
internal write buffer enables the data-ins to be regis-
tered one cycle later than the write address. The first
data-in burst is clocked with the rising edge of the
next K clock, and the second burst is timed to the
following rising edge of the K clock.
During the burst read operation, at the first burst the
data-outs are updated from output registers off the
second rising edge of the C clock (1.5 cycles later).
At the second burst, the data-outs are updated with
the third rising edge of the corresponding C clock
(see page 9). The K and K clocks are used to time
the data-outs whenever the C and C clocks are tied
high.
The device is operated with a single +1.8V power
supply and is compatible with HSTL I/O interfaces.
.
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IS61DDB22M18-250M3L 功能描述:靜態(tài)隨機(jī)存取存儲(chǔ)器 36M (2Mx18) 250ns DDR II Sync 靜態(tài)隨機(jī)存取存儲(chǔ)器 RoHS:否 制造商:Cypress Semiconductor 存儲(chǔ)容量:16 Mbit 組織:1 M x 16 訪(fǎng)問(wèn)時(shí)間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray
IS61DDB22M18A-250B4LI 功能描述:靜態(tài)隨機(jī)存取存儲(chǔ)器 36Mb, DDR II CIO Sync 靜態(tài)隨機(jī)存取存儲(chǔ)器, 2M x 18 RoHS:否 制造商:Cypress Semiconductor 存儲(chǔ)容量:16 Mbit 組織:1 M x 16 訪(fǎng)問(wèn)時(shí)間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray
IS61DDB22M18A-250M3L 功能描述:靜態(tài)隨機(jī)存取存儲(chǔ)器 36Mb 2Mx18 165ball RoHS:否 制造商:Cypress Semiconductor 存儲(chǔ)容量:16 Mbit 組織:1 M x 16 訪(fǎng)問(wèn)時(shí)間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray
IS61DDB22M36 制造商:ISSI 制造商全稱(chēng):Integrated Silicon Solution, Inc 功能描述:72 Mb (2M x 36 & 4M x 18) DDR-II (Burst of 2) CIO Synchronous SRAMs
IS61DDB22M36-250M3 制造商:ISSI 制造商全稱(chēng):Integrated Silicon Solution, Inc 功能描述:72 Mb (2M x 36 & 4M x 18) DDR-II (Burst of 2) CIO Synchronous SRAMs
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