參數(shù)資料
型號(hào): IS61C64AH
廠商: Integrated Silicon Solution, Inc.
英文描述: 8K x 8 High-Speed CMOS Static RAM(8K x 8 高速CMOS靜態(tài)RAM)
中文描述: 8K的× 8高速CMOS靜態(tài)RAM(8K的× 8高速的CMOS靜態(tài)RAM)的
文件頁(yè)數(shù): 1/8頁(yè)
文件大?。?/td> 46K
代理商: IS61C64AH
Integrated Silicon Solution, Inc.
SR035-1
I
05/12/99
1
ISSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any errors which
may appear in this publication. Copyright 1999, Integrated Silicon Solution, Inc.
FEATURES
High-speed access time: 15, 20, 25 ns
Automatic power-down when chip is
deselected
CMOS low power operation
— 450 mW (typical) operating
— 250
μ
W (typical) standby
TTL compatible interface levels
Single 5V power supply
Fully static operation: no clock or refresh
required
Three state outputs
Two Chip Enables (
CE1
and CE2) for
simple memory expansion
IS61C64AH
8K x 8 HIGH-SPEED CMOS STATIC RAM
MAY 1999
ISSI
DESCRIPTION
The
ISSI
IS61C64AH is a very high-speed, low power,
8192-word by 8-bit static RAM. It is fabricated using
ISSI
's
high-performance CMOS technology. This highly reliable pro-
cess coupled with innovative circuit design techniques, yields
access times as fast as 15 ns with low power consumption.
When
CE1
is HIGH or CE2 is LOW (deselected), the device
assumes a standby mode at which the power dissipation can
be reduced down to 250
μ
W (typical) with CMOS input levels.
Easy memory expansion is provided by using two Chip Enable
inputs,
CE1
and CE2. The active LOW Write Enable (
WE
)
controls both writing and reading of the memory.
The IS61C64AH is packaged in the JEDEC standard 28-pin,
SOJ and 330-mil SOP.
FUNCTIONAL BLOCK DIAGRAM
A0-A12
CE1
OE
WE
256 X 256
MEMORY ARRAY
DECODER
COLUMN I/O
CONTROL
CIRCUIT
GND
VCC
I/O
DATA
CIRCUIT
I/O0-I/O7
CE2
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