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參數(shù)資料
| 型號： | IS61C256AH-20JI |
| 廠商： | INTEGRATED SILICON SOLUTION INC |
| 元件分類： | DRAM |
| 英文描述： | 32K x 8 HIGH-SPEED CMOS STATIC RAM |
| 中文描述： | 32K X 8 STANDARD SRAM, 20 ns, PDSO28 |
| 封裝： | 0.300 INCH, PLASTIC, SOJ-28 |
| 文件頁數(shù)： | 7/8頁 |
| 文件大?。?/td> | 60K |
| 代理商： | IS61C256AH-20JI |
Integrated Silicon Solution, Inc. — 1-800-379-4774
SR020-1O
05/24/99
7
IS61C256AH
ISSI
DATA UNDEFINED
LOW
t
WC
VALID ADDRESS
t
PWE1
t
AW
t
HA
HIGH-Z
t
HD
t
SA
t
HZWE
ADDRESS
CE
WE
D
OUT
D
IN
OE
DATA
IN
VALID
t
LZWE
t
SD
CE_WR2.eps
WRITE CYCLE NO. 2
(
OE
is HIGH During Write Cycle)
(1,2)
WRITE CYCLE NO. 3
(
OE
is LOW During Write Cycle)
(1)
DATA UNDEFINED
t
WC
VALID ADDRESS
LOW
LOW
t
PWE2
t
AW
t
HA
HIGH-Z
t
HD
t
SA
t
HZWE
ADDRESS
CE
WE
D
OUT
D
IN
OE
DATA
IN
VALID
t
LZWE
t
SD
CE_WR3.eps
Notes:
1. The internal write time is defined by the overlap of
CE
LOW and
WE
LOW. All signals must be in valid states to initiate a Write,
but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the rising or falling
edge of the signal that terminates the Write.
2. I/O will assume the High-Z state if
OE
≥
V
IH
.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| IS61C256AH-20N | 32K x 8 HIGH-SPEED CMOS STATIC RAM |
| IS61C256AH-20NI | 32K x 8 HIGH-SPEED CMOS STATIC RAM |
| IS61C256AH-20T | 32K x 8 HIGH-SPEED CMOS STATIC RAM |
| IS61C256AH-20TI | 32K x 8 HIGH-SPEED CMOS STATIC RAM |
| IS61C256AH-25J | 32K x 8 HIGH-SPEED CMOS STATIC RAM |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| IS61C256AH20JT | 制造商:ISSI 功能描述:* |
| IS61C256AH-20N | 制造商:ISSI 制造商全稱:Integrated Silicon Solution, Inc 功能描述:32K x 8 HIGH-SPEED CMOS STATIC RAM |
| IS61C256AH-20NI | 制造商:ISSI 制造商全稱:Integrated Silicon Solution, Inc 功能描述:32K x 8 HIGH-SPEED CMOS STATIC RAM |
| IS61C256AH-20T | 制造商:ISSI 制造商全稱:Integrated Silicon Solution, Inc 功能描述:32K x 8 HIGH-SPEED CMOS STATIC RAM |
| IS61C256AH-20TI | 制造商:ISSI 制造商全稱:Integrated Silicon Solution, Inc 功能描述:32K x 8 HIGH-SPEED CMOS STATIC RAM |
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