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參數(shù)資料
| 型號： | IS61C256AH-12TI |
| 廠商： | INTEGRATED SILICON SOLUTION INC |
| 元件分類： | DRAM |
| 英文描述： | 32K x 8 HIGH-SPEED CMOS STATIC RAM |
| 中文描述： | 32K X 8 STANDARD SRAM, 12 ns, PDSO28 |
| 封裝： | TSOP1-28 |
| 文件頁數(shù)： | 6/8頁 |
| 文件大?。?/td> | 60K |
| 代理商： | IS61C256AH-12TI |
6
Integrated Silicon Solution, Inc. — 1-800-379-4774
SR020-1O
05/24/99
IS61C256AH
ISSI
WRITE CYCLE SWITCHING CHARACTERISTICS
(1,3)
(Over Operating Range)
-10
-12
Min.
-15
-20
-25
Symbol
t
WC
t
SCE
t
AW
Parameter
Min.
Max
Max.
Min.
Max.
Min.
Max.
Min.
Max.
Unit
Write Cycle Time
10
—
12
—
15
—
20
—
25
—
ns
CE
to Write End
9
—
10
—
10
—
13
—
15
—
ns
Address Setup Time
to Write End
9
—
10
—
12
—
15
—
20
—
ns
t
HA
Address Hold
from Write End
0
—
0
—
0
—
0
—
0
—
ns
t
SA
t
PWE
1
t
PWE
2
t
SD
t
HD
t
HZWE
(2)
t
LZWE
(2)
Address Setup Time
0
—
0
—
0
—
0
—
0
—
ns
WE
Pulse Width (
OE
LOW)
8
—
8
—
10
—
13
—
15
—
ns
WE
Pulse Width (
OE
HIGH)
6.5
—
7
—
8
—
10
—
12
—
ns
Data Setup to Write End
7
—
7
—
9
—
10
—
12
—
ns
Data Hold from Write End
0
—
0
—
0
—
0
—
0
—
ns
WE
LOW to High-Z Output
—
6
—
6
—
7
—
8
—
10
ns
WE
HIGH to Low-Z Output
0
—
0
—
0
—
0
—
0
—
ns
Notes:
1. Test conditions assume signal transition times of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V and
output loading specified in Figure 1.
2. Tested with the load in Figure 2. Transition is measured
±
500 mV from steady-state voltage. Not 100% tested.
3. The internal write time is defined by the overlap of
CE
LOW and
WE
LOW. All signals must be in valid states to initiate a Write,
but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the rising or falling
edge of the signal that terminates the write.
AC WAVEFORMS
WRITE CYCLE NO. 1 (
WE
Controlled)
(1,2)
DATA UNDEFINED
t
WC
VALID ADDRESS
t
SCE
t
PWE1
t
PWE2
t
AW
t
HA
HIGH-Z
t
HD
t
SA
t
HZWE
ADDRESS
CE
WE
D
OUT
D
IN
DATA
IN
VALID
t
LZWE
t
SD
CE_WR1.eps
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| IS61C256AH-15N | 32K x 8 HIGH-SPEED CMOS STATIC RAM |
| IS61C256AL-12TI | 32K x 8 HIGH-SPEED CMOS STATIC RAM |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| IS61C256AH-12TL | 制造商:Integrated Silicon Solution Inc 功能描述:SRAM Chip Async Single 5V 256K-Bit 32K x 8 12ns 28-Pin TSOP-I |
| IS61C256AH-12TLI | 制造商:Integrated Silicon Solution Inc 功能描述:SRAM Chip Async Single 5V 256K-Bit 32K x 8 12ns 28-Pin TSOP-I |
| IS61C256AH-12T-TR | 制造商:Integrated Silicon Solution Inc 功能描述:SRAM Chip Async Single 5V 256K-Bit 32K x 8 12ns 28-Pin TSOP-I T/R |
| IS61C256AH-15J | 功能描述:靜態(tài)隨機(jī)存取存儲器 256K 32Kx8 15ns 5v RoHS:否 制造商:Cypress Semiconductor 存儲容量:16 Mbit 組織:1 M x 16 訪問時間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
| IS61C256AH-15JI | 功能描述:靜態(tài)隨機(jī)存取存儲器 256K 32Kx8 15ns 5v RoHS:否 制造商:Cypress Semiconductor 存儲容量:16 Mbit 組織:1 M x 16 訪問時間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
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