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參數(shù)資料
| 型號： | IS450 |
| 廠商： | Sharp Corporation |
| 英文描述： | OPIC LIGHT DETECTOR WITH BULLT-IN SIGNAL PROCESSING CIRCULT FOR LIGHT MODULATION SYSTEM |
| 中文描述： | 海外私人投資公司與BULLT光檢測器的信號的光調(diào)制系統(tǒng)處理CIRCULT |
| 文件頁數(shù)： | 1/14頁 |
| 文件大?。?/td> | 490K |
| 代理商： | IS450 |
Integrated Circuit Solution Inc.
1
SSR011-0B
ICSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any errors
which may appear in this publication. Copyright 2000, Integrated Circuit Solution Inc.
FEATURES
Internal self-timed write cycle
Individual Byte Write Control and Global Write
Clock controlled, registered address, data and
control
Pentium or linear burst sequence control
using MODE input
Three chip enables for simple depth expansion
and address pipelining
Common data inputs and data outputs
JEDEC 100-Pin LQFP and
119-pin PBGA package
Single +3.3V, +10%, –5% power supply
Power-down snooze mode
DESCRIPTION
The
ICSI
IS61SP12832 is a high-speed, low-power synchro-
nous static RAM designed to provide a burstable, high-perfor-
mance, secondary cache for the Pentium, 680X0, and
PowerPC microprocessors. It is organized as 131,072
words by 32 bits, fabricated with
ICSI
's advanced CMOS
technology. The device integrates a 2-bit burst counter, high-
speed SRAM core, and high-drive capability outputs into a
single monolithic circuit. All synchronous inputs pass through
registers controlled by a positive-edge-triggered single clock
input.
Write cycles are internally self-timed and are initiated by the
rising edge of the clock input. Write cycles can be from one to
four bytes wide as controlled by the write control inputs.
Separate byte enables allow individual bytes to be written.
BW1
controls DQa,
BW2
controls DQb,
BW3
controls DQc,
BW4
controls DQd, conditioned by
BWE
being LOW. A LOW
on
GW
input would cause all bytes to be written.
Bursts can be initiated with either
ADSP
(Address Status
Processor) or
ADSC
(Address Status Cache Controller) input
pins. Subsequent burst addresses can be generated internally
by the IS61SP12832 and controlled by the
ADV
(burst address
advance) input pin.
The mode pin is used to select the burst sequence order,
Linear burst is achieved when this pin is tied LOW. Interleave
burst is achieved when this pin is tied HIGH or left floating.
IS61SP12832
128K x 32 SYNCHRONOUS
PIPELINED STATIC RAM
FAST ACCESS TIME
Symbol
Parameter
-166
-150
-133
-117
-5
Units
t
KQ
Clock Access Time
3.5
3.8
4
4
5
ns
t
KC
Cycle Time
6
6.7
7.5
8.5
10
ns
Frenquency
166
150
133
117
100
MHz
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| IS61SP12832-117TQ | 128K x 32 SYNCHRONOUS PIPELINED STATIC RAM |
| IS61SP12832-133B | 128K x 32 SYNCHRONOUS PIPELINED STATIC RAM |
| IS61SP12832-133TQ | 128K x 32 SYNCHRONOUS PIPELINED STATIC RAM |
| IS61SP12832-150B | 128K x 32 SYNCHRONOUS PIPELINED STATIC RAM |
| IS61SP12832-150TQ | 128K x 32 SYNCHRONOUS PIPELINED STATIC RAM |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| IS-450 | 制造商:Brainboxes 功能描述:Instashield PCI LP 4 x RS232 制造商:Brainboxes 功能描述:INTASHIELD PCI LP 4XRS232 制造商:BRAINBOXES 功能描述:INTASHIELD PCI LP 4XRS232 |
| IS452 | 制造商:Isocom Components 功能描述:Low i/pcurrent optocoupler,IS452 5300Vac |
| IS455 | 制造商:SHARP 制造商全稱:Sharp Electrionic Components 功能描述:Linear Output Type OPIC Light Detector |
| IS456 | 功能描述:LIGHT DETECTOR OPIC 660NM SMD RoHS:否 類別:傳感器，轉(zhuǎn)換器 >> 光學(xué) - 光電探測器 - 環(huán)境光傳感器 系列:* 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 產(chǎn)品變化通告:Product Discontinuation 25/Jun/2012 標(biāo)準(zhǔn)包裝:2,500 系列:- 帶接近傳感器:無 波長:- 電源電壓:1.7 V ~ 2 V 電流 - 暗（標(biāo)準(zhǔn)）:- 電流 - 光（典型值）:- 輸出類型:數(shù)字 - I²C 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:6-UDFN 裸露焊盤 包裝:帶卷 (TR) |
| IS457 | 制造商:SHARP 制造商全稱:Sharp Electrionic Components 功能描述:High Speed Response Type OPIC Light Detector |
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