參數(shù)資料
型號(hào)： IS43R16800A-6TL
廠商： INTEGRATED SILICON SOLUTION INC
元件分類： DRAM
英文描述： 8Meg x 16 128-MBIT DDR SDRAM
中文描述： 8M X 16 DDR DRAM, 0.7 ns, PDSO66
封裝： LEAD FREE, PLASTIC, TSOP2-66
文件頁(yè)數(shù)： 16/47頁(yè)
文件大小： 473K
代理商： IS43R16800A-6TL
16
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. 00A
04/04/06
ISSI
IS43R16800A-6
Write Operation
A Write command starts a burst from an activated row.
The Write command is depicted in the figure. As CK
goes High,
CS
,
WE
, and
CAS
are Low, while CKE and
RAS
are High. The values on the inputs BA0 and BA1
specify the bank to access, and the address inputs
specify the starting column in the open row. If Auto
Pre-charge is enabled in the Write command, the
open row will be pre-charged after completion of the
Write burst and time tWR. Unless stated otherwise, all
timing diagrams for Write operations have disabled
Auto Pre-charge.
The Write command in conjunction with Data Strobe
inputs causes data to be latched and placed in the
pipeline. The Low portion of the Data Strobe between
the Write command and the first rising edge of the
strobe is the Write Pre-amble; and the Low portion
following the last input data is the Write Post-amble.
A minimum time of tDQSS after the Write, the next
command can be NOP or Write. The data that is to be
written to the starting column specified in the Write
command will be latched upon the first rising edge of
Data Strobe input(s) LDQS, UDQS (x16) after that Write
command. On each Data Strobe transition from Low-to-
High or High-to-Low, the input values on the I/O are
sampled, and enter pipeline to be written in the pre-
determined burst sequence (see Write Burst, Consecu-
tive Write to Write, and Non-consecutive Write to Write).
A new Write command can be issued x cycles after a
previous Write command, where x is the number of pairs
of columns to input. By following a desired command
sequence, continuous data can be input with either whole
Write bursts or truncated Write bursts. Whenever a Write
burst finishes and no other commands have been
initiated, the I/O returns to High-Z.
A Write burst may be followed by Read command, with
or without truncating the Write burst. To avoid truncat-
ing the input data, the timing parameter tWTR should
be obeyed before issuing the Read command (see
Write to Read, Non-truncated). The period tWTR
begins on the first positive clock edge after the last
data input has been latched. The Write burst can be
truncated deliberately by using the Data Mask feature
and a Read command with an earlier timing (see Write
to Read, Truncated).
If Auto Pre-charge is not enabled in the Write burst,
the Pre-charge command can be issued separately
some time following the Write command. The proce-
dure to execute it is similar to the procedure to transi-
tion from a Write burst to a Read burst. To avoid
truncating the input data, the timing parameter tWR
should be obeyed before issuing the Pre-charge com-
mand (see Write to Pre-charge, Non-truncated). The
period tWR begins on the first positive clock edge after
the last data input has been latched. The Write burst
can be truncated deliberately by using the Data Mask
feature and a Pre-charge command with an earlier timing
(see Write to Pre-charge, Truncated). After the Pre-
charge command, it is necessary to wait until tRP has
been met before issuing a new command to the same
bank.
Power Down Operation
When the DDR SDRAM enters Power Down mode,
power consumption is greatly reduced. To enter the
mode, several conditions must be met. There must be
neither a Read operation, nor a Write operation
underway in the device at CK positive edge n – 1, with
CKE stable High. Prior to CK positive edge n, CKE
should go Low. A Power Down mode is entered if the
appropriate command is issued as CK n goes High. (If
the command at CK n is Auto Refresh, the SDRAM
enters Self Refresh mode.) If the command at CK n is
NOP or Deselect, the device will enter Pre-charge Power
Down mode or Active Power Down mode. While in a
Power Down mode, CKE must be stable Low, and CK
and
CK
signals maintained, while other inputs are
ignored. Pre-charge Power Down mode conserves
additional power by freezing the DLL. To exit the Power
Down mode, normal voltages and clock frequency are
applied. Prior to CK positive edge n, CKE should go
High. A NOP or Deselect command at CK n, allows a
valid command to be issued at CK positive edge n + 1.
(If exiting Self Refresh mode, the DLL is automatically
enabled, and the device must be prepared according to
the section describing Self Refresh.)
Pre-charge Operation
When this command is issued, either a particular
bank, or all four banks will be de-activated after a time
period of tRP. The bank(s) will be available for a row
access until that time has occurred. The Pre-charge
command is depicted in the figure. As CK goes High,
CS
,
RAS
, and
WE
are Low, while CKE and
CAS
are
High. The values on the address inputs are Don’t Care,
except for the input A10 (x16), which determines whether
a single bank is selected for Pre-charge, or all four
banks. If A10 is Low, the inputs BA0 and BA1 select the
single bank; however, if A10 is High, BA0 and BA1 are
Don’t Care. Once any bank has been pre-charged, it
becomes idle. Before any row can have a Read or Write
access, it must be activated.
相關(guān)PDF資料
PDF描述
IS43R16800A1 8Meg x 16 128-MBIT DDR SDRAM
IS43R16800A1-5TL 8Meg x 16 128-MBIT DDR SDRAM
IS43R32400A 4Meg x 32 128-MBIT DDR SDRAM
IS43R32400A-5B 4Meg x 32 128-MBIT DDR SDRAM
IS43R32400A-5BL 4Meg x 32 128-MBIT DDR SDRAM
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