參數(shù)資料
型號： IS42S81600B-7TL
廠商： INTEGRATED SILICON SOLUTION INC
元件分類： DRAM
英文描述： 16Meg x 8, 8Meg x16 128-MBIT SYNCHRONOUS DRAM
中文描述： 16M X 8 SYNCHRONOUS DRAM, 5.4 ns, PDSO54
封裝： 0.400 INCH, LEAD FREE, TSOP2-54
文件頁數(shù)： 19/60頁
文件大?。?/td> 585K
代理商： IS42S81600B-7TL
Integrated Silicon Solution, Inc. — www.issi.com —
1-800-379-4774
Rev. E
05/01/06
19
ISSI
IS42S81600B, IS42S16800B
FUNCTIONAL DESCRIPTION
The 128Mb SDRAMs are quad-bank DRAMs which operate
at 3.3V and include a synchronous interface (all signals are
registered on the positive edge of the clock signal, CLK).
Each of the 33,554,432-bit banks is organized as 4,096
rows by 512 columns by 16 bits or 4,096 rows by 1,024
columns by 8 bits.
Read and write accesses to the SDRAM are burst oriented;
accesses start at a selected location and continue for a
programmed number of locations in a programmed
sequence. Accesses begin with the registration of an AC-
TIVE command which is then followed by a READ or WRITE
command. The address bits registered coincident with the
ACTIVE command are used to select the bank and row to
be accessed
(BA0 and BA1 select the bank, A0-A11 select the row)
.
The address bits
A0-A9 (x8); A0-A8 (x16)
registered coincident
with the READ or WRITE command are used to select the
starting column location for the burst access.
Prior to normal operation, the SDRAM must be initialized.
The following sections provide detailed information covering
device initialization, register definition, command
descriptions and device operation.
Initialization
SDRAMs must be powered up and initialized in a
predefined manner.
The 128M SDRAM is initialized after the power is applied to
V
DD
and V
DDQ
(simultaneously) and the clock is stable with
DQM High and CKE High.
A 100μs delay is required prior to issuing any command
other than a
COMMAND INHIBIT
or a
NOP
. The COMMAND
INHIBIT or NOP may be applied during the 100us period and
should continue at least through the end of the period.
With at least one COMMAND INHIBIT or NOP command
having been applied, a PRECHARGE command should be
applied once the 100μs delay has been satisfied. All banks
must be precharged. This will leave all banks in an idle state
after which at least two
AUTO REFRESH
cycles must be
performed. After the
AUTO REFRESH
cycles are complete,
the SDRAM is then ready for mode register programming.
The mode register should be loaded prior to applying any
operational command because it will power up in an un-
known state.
相關(guān)PDF資料
PDF描述
IS42S81600B-7TLI 16Meg x 8, 8Meg x16 128-MBIT SYNCHRONOUS DRAM
IS42S32200B 512K Bits x 32 Bits x 4 Banks (64-MBIT) SYNCHRONOUS DYNAMIC RAM
IS42S32200B-6T 512K Bits x 32 Bits x 4 Banks (64-MBIT) SYNCHRONOUS DYNAMIC RAM
IS42S32200B-6TI 512K Bits x 32 Bits x 4 Banks (64-MBIT) SYNCHRONOUS DYNAMIC RAM
IS42S32200B-6TL 512K Bits x 32 Bits x 4 Banks (64-MBIT) SYNCHRONOUS DYNAMIC RAM
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
IS42S81600B-7TLI 功能描述:動態(tài)隨機存取存儲器 128M 16Mx8 143Mhz RoHS:否 制造商:ISSI 數(shù)據(jù)總線寬度:16 bit 組織:1 M x 16 封裝 / 箱體:SOJ-42 存儲容量:16 MB 最大時鐘頻率: 訪問時間:50 ns 電源電壓-最大:7 V 電源電壓-最小:- 1 V 最大工作電流:90 mA 最大工作溫度:+ 85 C 封裝:Tube
IS42S81600B-7TLI-TR 功能描述:動態(tài)隨機存取存儲器 128M 16Mx8 143Mhz RoHS:否 制造商:ISSI 數(shù)據(jù)總線寬度:16 bit 組織:1 M x 16 封裝 / 箱體:SOJ-42 存儲容量:16 MB 最大時鐘頻率: 訪問時間:50 ns 電源電壓-最大:7 V 電源電壓-最小:- 1 V 最大工作電流:90 mA 最大工作溫度:+ 85 C 封裝:Tube
IS42S81600B-7TL-TR 功能描述:動態(tài)隨機存取存儲器 128M 16Mx8 143Mhz RoHS:否 制造商:ISSI 數(shù)據(jù)總線寬度:16 bit 組織:1 M x 16 封裝 / 箱體:SOJ-42 存儲容量:16 MB 最大時鐘頻率: 訪問時間:50 ns 電源電壓-最大:7 V 電源電壓-最小:- 1 V 最大工作電流:90 mA 最大工作溫度:+ 85 C 封裝:Tube
IS42S81600B-7T-TR 功能描述:動態(tài)隨機存取存儲器 128M 16Mx8 143Mhz RoHS:否 制造商:ISSI 數(shù)據(jù)總線寬度:16 bit 組織:1 M x 16 封裝 / 箱體:SOJ-42 存儲容量:16 MB 最大時鐘頻率: 訪問時間:50 ns 電源電壓-最大:7 V 電源電壓-最小:- 1 V 最大工作電流:90 mA 最大工作溫度:+ 85 C 封裝:Tube
IS42S81600D 制造商:ISSI 制造商全稱:Integrated Silicon Solution, Inc 功能描述:16Meg x 8, 8Meg x16 128-MBIT SYNCHRONOUS DRAM
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