參數(shù)資料
型號: IS42S32400B-7TLI
廠商: INTEGRATED SILICON SOLUTION INC
元件分類: DRAM
英文描述: 4Meg x 32 128-MBIT SYNCHRONOUS DRAM
中文描述: 4M X 32 SYNCHRONOUS DRAM, 5.4 ns, PDSO86
封裝: LEAD FREE, TSOP2-86
文件頁數(shù): 5/60頁
文件大?。?/td> 644K
代理商: IS42S32400B-7TLI
Integrated Silicon Solution, Inc. — www.issi.com —
1-800-379-4774
PRELIMINARY INFORMATION
Rev. 00G
06/15/06
5
ISSI
IS42S32400B
PIN FUNCTIONS
Symbol
Type
Function (In Detail)
A0-A11
Input Pin
Address Inputs: A0-A11 are sampled during the ACTIVE
command (row-address A0-A11) and READ/WRITE command (column address A0-
A7), with A10 defining auto precharge) to select one location out of the memory array in
the respective bank. A10 is sampled during a PRECHARGE command to determine if
all banks are to be precharged (A10 HIGH) or bank selected by
BA0, BA1 (LOW). The address inputs also provide the op-code during a LOAD MODE
REGISTER command.
BA0, BA1
Input Pin
Bank Select Address: BA0 and BA1 defines which bank the ACTIVE, READ, WRITE or
PRECHARGE command is being applied.
CAS
Input Pin
CAS
, in conjunction with the
RAS
and
WE
, forms the device command. See the
"Command Truth Table" for details on device commands.
CKE
Input Pin
The CKE input determines whether the CLK input is enabled. The next rising edge of the
CLK signal will be valid when is CKE HIGH and invalid when LOW. When CKE is LOW,
the device will be in either power-down mode, clock suspend mode, or self refresh
mode.
CKE is an
asynchronous i
nput.
CLK
Input Pin
CLK is the master clock input for this device. Except for CKE, all inputs to this device
are acquired in synchronization with the rising edge of this pin.
CS
Input Pin
The
CS
input determines whether command input is enabled within the device.
Command input is enabled when
CS
is LOW, and disabled with
CS
is HIGH. The device
remains in the previous state when
CS
is HIGH.
DQM0-DQM3
Input Pin
DQM0 - DQM3 control the four bytes of the I/O buffers (DQ0-DQ31). In read
mode, DQMn control the output buffer. When DQMn is LOW, the corresponding buffer
byte is enabled, and when HIGH, disabled. The outputs go to the HIGH impedance
state whenDQMn is HIGH. This function corresponds to
OE
in conventional DRAMs. In
write mode, DQMn control the input buffer. When DQMn is LOW, the corresponding
buffer byte is enabled, and data can be written to the device. When DQMn is HIGH,
input data is masked and cannot be written to the device.
DQ0-DQ31
Input/Output Pin
Data on the Data Bus is latched on these pins during Write commands, and buffered
after Read commands.
RAS
Input Pin
RAS
, in conjunction with
CAS
and
WE
, forms the device command. See the "Command
Truth Table" item for details on device commands.
WE
Input Pin
WE
, in conjunction with
RAS
and
CAS
, forms the device command. See the "Command
Truth Table" item for details on device commands.
V
DDQ
Power Supply Pin
V
DDQ
is the output buffer power supply.
V
DD
Power Supply Pin
V
DD
is the device internal power supply.
V
SSQ
Power Supply Pin
V
SSQ
is the output buffer ground.
V
SS
Power Supply Pin
V
SS
is the device internal ground.
相關(guān)PDF資料
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IS42S32400B 4Meg x 32 128-MBIT SYNCHRONOUS DRAM
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
IS42S32400B-7TLI U867 制造商:Integrated Silicon Solution Inc 功能描述:
IS42S32400B-7TLI-TR 功能描述:動態(tài)隨機(jī)存取存儲器 128M (4Mx32) 143MHz Industrial Temp RoHS:否 制造商:ISSI 數(shù)據(jù)總線寬度:16 bit 組織:1 M x 16 封裝 / 箱體:SOJ-42 存儲容量:16 MB 最大時鐘頻率: 訪問時間:50 ns 電源電壓-最大:7 V 電源電壓-最小:- 1 V 最大工作電流:90 mA 最大工作溫度:+ 85 C 封裝:Tube
IS42S32400B-7TL-TR 功能描述:動態(tài)隨機(jī)存取存儲器 128M (4Mx32) 143MHz Commercial Temp RoHS:否 制造商:ISSI 數(shù)據(jù)總線寬度:16 bit 組織:1 M x 16 封裝 / 箱體:SOJ-42 存儲容量:16 MB 最大時鐘頻率: 訪問時間:50 ns 電源電壓-最大:7 V 電源電壓-最小:- 1 V 最大工作電流:90 mA 最大工作溫度:+ 85 C 封裝:Tube
IS42S32400B-7T-TR 制造商:Integrated Silicon Solution Inc 功能描述:IC SDRAM 128MBIT 143MHZ 86TSOP
IS42S32400D 制造商:ISSI 制造商全稱:Integrated Silicon Solution, Inc 功能描述:4Meg x 32 128-MBIT SYNCHRONOUS DRAM