參數(shù)資料
型號: IS42S32400B-6B
廠商: INTEGRATED SILICON SOLUTION INC
元件分類: DRAM
英文描述: 4Meg x 32 128-MBIT SYNCHRONOUS DRAM
中文描述: 4M X 32 SYNCHRONOUS DRAM, 5.4 ns, PBGA90
封裝: FBGA-90
文件頁數(shù): 16/60頁
文件大?。?/td> 644K
代理商: IS42S32400B-6B
ISSI
16
Integrated Silicon Solution, Inc. — www.issi.com —
1-800-379-4774
PRELIMINARY INFORMATION
Rev. 00G
06/15/06
IS42S32400B
AC ELECTRICAL CHARACTERISTICS
(1,2,3)
-6
-7
Symbol
Parameter
Min.
Max.
Min.
Max.
Units
t
CK3
t
CK2
Clock Cycle Time
CAS
Latency = 3
CAS
Latency = 2
6
8
7
ns
ns
10
t
AC3
t
AC2
Access Time From CLK
CAS
Latency = 3
CAS
Latency = 2
5.4
6.5
5.4
6.5
ns
ns
t
CHI
CLK HIGH Level Width
2.5
2.5
ns
t
CL
CLK LOW Level Width
2.5
2.5
ns
t
OH3
t
OH2
Output Data Hold Time
CAS
Latency = 3
CAS
Latency = 2
2.7
2.7
2.7
3
ns
ns
t
LZ
Output LOW Impedance Time
0
0
ns
t
HZ
Output HIGH Impedance Time
2.7
5.4
2.7
5.4
ns
t
DS
Input Data Setup Time
(2)
1.5
1.5
ns
t
DH
Input Data Hold Time
(2)
0.8
0.8
ns
t
AS
Address Setup Time
(2)
1.5
1.5
ns
t
AH
Address Hold Time
(2)
0.8
0.8
ns
t
CKS
CKE Setup Time
(2)
1.5
1.5
ns
t
CKH
CKE Hold Time
(2)
0.8
0.8
ns
t
CS
Command Setup Time (
CS
,
RAS
,
CAS
,
WE
, DQM)
(2)
1.5
1.5
ns
t
CH
Command Hold Time (
CS
,
RAS
,
CAS
,
WE
, DQM)
(2)
0.8
0.8
ns
t
RC
Command Period (REF to REF / ACT to ACT)
60
67.5
ns
t
RAS
Command Period (ACT to PRE)
42
100K
45
100K
ns
t
RP
Command Period (PRE to ACT)
18
20
ns
t
RCD
Active Command To Read / Write Command Delay Time
18
20
ns
t
RRD
Command Period (ACT [0] to ACT[1])
12
14
ns
t
DPL
Input Data To Precharge
Command Delay time
12
14
ns
t
DAL
Input Data To Active / Refresh
Command Delay time (During Auto-Precharge)
30
34
ns
t
MRD
Mode Register Program Time
12
15
ns
t
DDE
Power Down Exit Setup Time
6
7.5
ns
t
XSR
Self-Refresh Exit Time
70
70
ns
t
T
Transition Time
1
10
1
10
ns
t
REF
Notes:
1. The power-on sequence must be executed before starting memory operation.
2. Measured with t
T
= 1 ns. If clock rising time is longer than 1ns, (t
R
/2 - 0.5) ns should be added to the parameter.
3.
The reference level is 1.4V when measuring input signal timing. Rise and fall times are measured between V
IH
(min.) and V
IL
(max).
Refresh Cycle Time (4096)
64
64
ms
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