參數(shù)資料
型號(hào): IS42S32200C1-6TL
廠商: INTEGRATED SILICON SOLUTION INC
元件分類: DRAM
英文描述: 512K Bits x 32 Bits x 4 Banks (64-MBIT) SYNCHRONOUS DYNAMIC RAM
中文描述: 2M X 32 SYNCHRONOUS DRAM, 5.5 ns, PDSO86
封裝: 0.400 INCH, LEAD FREE, PLASTIC, TSOP2-86
文件頁(yè)數(shù): 30/59頁(yè)
文件大小: 623K
代理商: IS42S32200C1-6TL
IS42S32200C1
ISSI
30
Integrated Silicon Solution, Inc. — www.issi.com —
1-800-379-4774
Rev. 00E
05/18/06
DON'T CARE
CLK
CKE
COMMAND
ADDRESS
DQ
T0
T1
T2
T3
T4
T5
NOP
WRITE
NOP
NOP
COL n
D
IN
n
D
IN
n+1
D
IN
n+2
INTERNAL
CLOCK
DON'T CARE
CLK
CKE
COMMAND
ADDRESS
DQ
T0
T1
T2
T3
T4
T5
T6
READ
NOP
NOP
NOP
NOP
NOP
BANK a,
COL n
D
OUT
n
D
OUT
n+1
D
OUT
n+2
D
OUT
n+3
INTERNAL
CLOCK
CLOCK SUSPEND
Clock suspend mode occurs when a column access/burst
is in progress and CKE is registered LOW. In the clock
suspend mode, the internal clock is deactivated, “freezing”
the synchronous logic.
For each positive clock edge on which CKE is sampled
LOW, the next internal positive clock edge is suspended.
Any command or data present on the input pins at the time
of a suspended internal clock edge is ignored; any data
present on the DQ pins remains driven; and burst counters
are not incremented, as long as the clock is suspended.
(See following examples.)
Clock suspend mode is exited by registering CKE HIGH;
the internal clock and related operation will resume on the
subsequent positive clock edge.
Clock Suspend During WRITE Burst
Clock Suspend During READ Burst
Burst Length 4 or greater DQM is low.
CAS Latency=2. Burst Length =4 or greater. DQM is low.
相關(guān)PDF資料
PDF描述
IS42S32200C1-6TLI 512K Bits x 32 Bits x 4 Banks (64-MBIT) SYNCHRONOUS DYNAMIC RAM
IS42S32200C1-7B 512K Bits x 32 Bits x 4 Banks (64-MBIT) SYNCHRONOUS DYNAMIC RAM
IS42S32200C1-7BI 512K Bits x 32 Bits x 4 Banks (64-MBIT) SYNCHRONOUS DYNAMIC RAM
IS42S32200C1-7BL 512K Bits x 32 Bits x 4 Banks (64-MBIT) SYNCHRONOUS DYNAMIC RAM
IS42S32200C1-7BLI 512K Bits x 32 Bits x 4 Banks (64-MBIT) SYNCHRONOUS DYNAMIC RAM
相關(guān)代理商/技術(shù)參數(shù)
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