參數(shù)資料
型號： IS42S32200C1-6BL
廠商： INTEGRATED SILICON SOLUTION INC
元件分類： DRAM
英文描述： 512K Bits x 32 Bits x 4 Banks (64-MBIT) SYNCHRONOUS DYNAMIC RAM
中文描述： 2M X 32 SYNCHRONOUS DRAM, 5.5 ns, PBGA90
封裝： 8 X 13 MM, 0.80 MM PITCH, LEAD FREE, MINI, FBGA-90
文件頁數(shù)： 13/59頁
文件大小： 623K
代理商： IS42S32200C1-6BL
IS42S32200C1
ISSI
Integrated Silicon Solution, Inc. — www.issi.com —
1-800-379-4774
Rev. 00E
05/18/06
13
FUNCTIONAL DESCRIPTION
The 64Mb SDRAMs 512K x 32 x 4 banks) are quad-bank
DRAMs which operate at 3.3V and include a synchronous
interface (all signals are registered on the positive edge of
the clock signal, CLK). Each of the 16,777,216-bit banks
is organized as 2,048 rows by 256 columns by 32bits.
Read and write accesses to the SDRAM are burst oriented;
accesses start at a selected location and continue for a
programmed number of locations in a programmed
sequence. Accesses begin with the registration of an
ACTIVE command which is then followed by a READ or
WRITE command. The address bits registered coincident
with the ACTIVE command are used to select the bank
and row to be accessed
(BA0 and BA1 select the bank, A0-A10
select the row)
. The address bits
(A0-A7)
registered coincident
with the READ or WRITE command are used to select the
starting column location for the burst access.
Prior to normal operation, the SDRAM must be initialized.
The following sections provide detailed information covering
device initialization, register definition, command
descriptions and device operation.
Initialization
SDRAMs must be powered up and initialized in a
predefined manner.
The 64M SDRAM is initialized after the power is applied
to V
DD
and V
DDQ
(simultaneously) and the clock is stable.
A 100μs delay is required prior to issuing any command
other than a
COMMAND INHIBIT
or a
NOP
. The COMMAND
INHIBIT or NOP may be applied during the 100us period
and continue should at least through the end of the period.
With at least one COMMAND INHIBIT or NOP command
having been applied, a PRECHARGE command should be
applied once the 100μs delay has been satisfied. All
banks must be precharged. This will leave all banks in an
idle idle state where two
AUTO REFRESH
cycles must be
performed. After the
AUTO REFRESH
cycles are complete,
the SRDRAM is then ready for mode register programming.
The mode register should be loaded prior to applying any
operational command because it will power up in an
unknown state.
相關(guān)PDF資料
PDF描述
IS42S32200C1-6T 512K Bits x 32 Bits x 4 Banks (64-MBIT) SYNCHRONOUS DYNAMIC RAM
IS42S32200C1-6TI 512K Bits x 32 Bits x 4 Banks (64-MBIT) SYNCHRONOUS DYNAMIC RAM
IS42S32200C1-6TL 512K Bits x 32 Bits x 4 Banks (64-MBIT) SYNCHRONOUS DYNAMIC RAM
IS42S32200C1-6TLI 512K Bits x 32 Bits x 4 Banks (64-MBIT) SYNCHRONOUS DYNAMIC RAM
IS42S32200C1-7B 512K Bits x 32 Bits x 4 Banks (64-MBIT) SYNCHRONOUS DYNAMIC RAM
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
IS42S32200C1-6BLI 制造商:Integrated Silicon Solution Inc 功能描述:DRAM Chip SDRAM 64M-Bit 2Mx32 3.3V 90-Pin Mini-BGA
IS42S32200C1-6T 功能描述:動態(tài)隨機存取存儲器 64M 2Mx32 166Mhz RoHS:否 制造商:ISSI 數(shù)據(jù)總線寬度:16 bit 組織:1 M x 16 封裝 / 箱體:SOJ-42 存儲容量:16 MB 最大時鐘頻率: 訪問時間:50 ns 電源電壓-最大:7 V 電源電壓-最小:- 1 V 最大工作電流:90 mA 最大工作溫度:+ 85 C 封裝:Tube
IS42S32200C1-6TI 制造商:ISSI 制造商全稱:Integrated Silicon Solution, Inc 功能描述:512K Bits x 32 Bits x 4 Banks (64-MBIT) SYNCHRONOUS DYNAMIC RAM
IS42S32200C1-6TL 功能描述:動態(tài)隨機存取存儲器 64M 2Mx32 166Mhz RoHS:否 制造商:ISSI 數(shù)據(jù)總線寬度:16 bit 組織:1 M x 16 封裝 / 箱體:SOJ-42 存儲容量:16 MB 最大時鐘頻率: 訪問時間:50 ns 電源電壓-最大:7 V 電源電壓-最小:- 1 V 最大工作電流:90 mA 最大工作溫度:+ 85 C 封裝:Tube
IS42S32200C1-6TLI 功能描述:動態(tài)隨機存取存儲器 64M (2Mx32) 166MHz Industrial Temp RoHS:否 制造商:ISSI 數(shù)據(jù)總線寬度:16 bit 組織:1 M x 16 封裝 / 箱體:SOJ-42 存儲容量:16 MB 最大時鐘頻率: 訪問時間:50 ns 電源電壓-最大:7 V 電源電壓-最小:- 1 V 最大工作電流:90 mA 最大工作溫度:+ 85 C 封裝:Tube
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