- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄377551 > IS42S32200B-7T (INTEGRATED SILICON SOLUTION INC) 512K Bits x 32 Bits x 4 Banks (64-MBIT) SYNCHRONOUS DYNAMIC RAM PDF資料下載
參數(shù)資料
| 型號： | IS42S32200B-7T |
| 廠商： | INTEGRATED SILICON SOLUTION INC |
| 元件分類： | DRAM |
| 英文描述： | 512K Bits x 32 Bits x 4 Banks (64-MBIT) SYNCHRONOUS DYNAMIC RAM |
| 中文描述： | 2M X 32 SYNCHRONOUS DRAM, 6.5 ns, PDSO86 |
| 封裝： | 0.400 INCH, PLASTIC, TSOP2-86 |
| 文件頁數(shù)： | 33/56頁 |
| 文件大?。?/td> | 537K |
| 代理商： | IS42S32200B-7T |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁當(dāng)前第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁
IS42S32200B
ISSI
Integrated Silicon Solution, Inc. — www.issi.com —
1-800-379-4774
Rev. 00C
09/29/03
33
AC ELECTRICAL CHARACTERISTICS
(1,2,3)
-6
-7
Symbol
Parameter
Min. Max.
Min. Max.
Units
t
CK3
t
CK2
Clock Cycle Time
CAS
Latency = 3
CAS
Latency = 2
6
—
—
7
10
—
—
ns
ns
10
t
AC3
t
AC2
Access Time From CLK
(4)
CAS
Latency = 3
CAS
Latency = 2
—
—
5.5
7.5
—
—
6.5
8
ns
ns
t
CHI
CLK HIGH Level Width
2.5
—
3
—
ns
t
CL
CLK LOW Level Width
2.5
—
3
—
ns
t
OH
Output Data Hold Time
2
—
2
—
ns
t
LZ
Output LOW Impedance Time
1
—
1
—
ns
t
HZ3
t
HZ2
Output HIGH Impedance Time
(5)
CAS
Latency = 3
—
—
5.5
7.5
—
—
5.5
8
ns
ns
CAS
Latency = 2
t
DS
Input Data Setup Time
1.5
—
2
—
ns
t
DH
Input Data Hold Time
1
—
1
—
ns
t
AS
Address Setup Time
1.5
—
1.5
—
ns
t
AH
Address Hold Time
1
—
1
—
ns
t
CKS
CKE Setup Time
1.5
—
2
—
ns
t
CKH
CKE Hold Time
1
—
1
—
ns
t
CKA
CKE to CLK Recovery Delay Time
1CLK+6
—
1CLK+7
—
ns
t
CS
Command Setup Time (
CS
,
RAS
,
CAS
,
WE
, DQM)
1.5
—
2
—
ns
t
CH
Command Hold Time (
CS
,
RAS
,
CAS
,
WE
, DQM)
1
—
1
—
ns
t
RC
Command Period (REF to REF / ACT to ACT)
60
—
70
—
ns
t
RAS
Command Period (ACT to PRE)
42
120,000
48
120,000
ns
t
RP
Command Period (PRE to ACT)
18
—
20
—
ns
t
RCD
Active Command To Read / Write Command Delay Time
18
—
20
—
ns
t
RRD
Notes:
1. An initial pause of 100us is required after power up, followed by two AUTO REFRESH commands, before proper device
operation is ensured. (Vdd and VddQ must be powered up simultaneously. GND and GNDQ must be at same potential.) The
two AUTO REFRESH command wake-ups should be repeated anytime the t
REF
refresh requirement is exceeded.
2. Measured with t
T
= 1 ns.
3. The reference level is 1.5V when measuring input signal timing. Rise/fall times are measured between V
IH
(min.) and V
IL
(max.).
4. Access time is measured at 1.5V with the load shown in the figure below.
5. The time t
HZ
(max.) is defined as the time required for the output voltage to transition by ± 200 mV from V
OH
(min.) or V
OL
(max.)
when the output is in the high impedance state.
6. CLK must be toggled a minimum of two times during this period.
Command Period (ACT [0] to ACT[1])
12
—
14
—
ns
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| IS42S32200B-7TI | 512K Bits x 32 Bits x 4 Banks (64-MBIT) SYNCHRONOUS DYNAMIC RAM |
| IS42S32200B-7TL | 512K Bits x 32 Bits x 4 Banks (64-MBIT) SYNCHRONOUS DYNAMIC RAM |
| IS42S32200B-7TLI | 512K Bits x 32 Bits x 4 Banks (64-MBIT) SYNCHRONOUS DYNAMIC RAM |
| IS42S32200C1 | 512K Bits x 32 Bits x 4 Banks (64-MBIT) SYNCHRONOUS DYNAMIC RAM |
| IS42S32200C1-55T | 512K Bits x 32 Bits x 4 Banks (64-MBIT) SYNCHRONOUS DYNAMIC RAM |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| IS42S32200B-7TI | 制造商:Integrated Silicon Solution Inc 功能描述:DRAM Chip SDRAM 64M-Bit 2Mx32 3.3V 86-Pin TSOP-II |
| IS42S32200B-7TI-TR | 制造商:Integrated Silicon Solution Inc 功能描述:DRAM Chip SDRAM 64M-Bit 2Mx32 3.3V 86-Pin TSOP-II T/R |
| IS42S32200B-7TL | 制造商:ISSI 制造商全稱:Integrated Silicon Solution, Inc 功能描述:512K Bits x 32 Bits x 4 Banks (64-MBIT) SYNCHRONOUS DYNAMIC RAM |
| IS42S32200B-7TLI | 制造商:ISSI 制造商全稱:Integrated Silicon Solution, Inc 功能描述:512K Bits x 32 Bits x 4 Banks (64-MBIT) SYNCHRONOUS DYNAMIC RAM |
| IS42S32200B-7T-TR | 制造商:Integrated Silicon Solution Inc 功能描述:DRAM Chip SDRAM 64M-Bit 2Mx32 3.3V 86-Pin TSOP-II T/R |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。