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參數(shù)資料
| 型號： | IS42S32200B-6TL |
| 廠商： | INTEGRATED SILICON SOLUTION INC |
| 元件分類： | DRAM |
| 英文描述： | 512K Bits x 32 Bits x 4 Banks (64-MBIT) SYNCHRONOUS DYNAMIC RAM |
| 中文描述： | 2M X 32 SYNCHRONOUS DRAM, 5.5 ns, PDSO86 |
| 封裝： | 0.400 INCH, LEAD FREE, PLASTIC, TSOP2-86 |
| 文件頁數(shù)： | 14/56頁 |
| 文件大?。?/td> | 537K |
| 代理商： | IS42S32200B-6TL |
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IS42S32200B
ISSI
14
Integrated Silicon Solution, Inc. — www.issi.com —
1-800-379-4774
Rev. 00C
09/29/03
DON'T CARE
UNDEFINED
CLK
COMMAND
DQ
READ
NOP
NOP
NOP
CAS Latency - 3
t
AC
t
OH
D
OUT
T0
T1
T2
T3
T4
t
LZ
CLK
COMMAND
DQ
READ
NOP
NOP
CAS Latency - 2
t
AC
t
OH
D
OUT
T0
T1
T2
T3
t
LZ
CAS Latency
CAS Latency
The CAS latency is the delay, in clock cycles, between the
registration of a READ command and the availability of the first
piece of output data. The latency can be set to two or three clocks.
If a READ command is registered at clock edge n, and the
latency is m clocks, the data will be available by clock
edge n + m. The DQs will start driving as a result of the
clock edge one cycle earlier (n + m 1), and provided that
the relevant access times are met, the data will be valid
by clock edge n + m. For example, assuming that the
clock cycle time is such that all relevant access times are
met, if a READ command is registered at T0 and the
latency is programmed to two clocks, the DQs will start
driving after T1 and the data will be valid by T2, as shown
in CAS Latency diagrams. The
Allowable Operating
Frequency
table indicates the operating frequencies at
which each CAS latency setting can be used.
Reserved states should not be used as unknown operation
or incompatibility with future versions may result.
Operating Mode
The normal operating mode is selected by setting M7 and M8
to zero; the other combinations of values for M7 and M8 are
CAS Latency
Allowable Operating Frequency (MHz)
Speed
CAS Latency = 2
CAS Latency = 3
6
—
166
7
100
143
reserved for future use and/or test modes. The programmed
burst length applies to both READ and WRITE bursts.
Test modes and reserved states should not be used
because unknown operation or incompatibility with future
versions may result.
Write Burst Mode
When M9 = 0, the burst length programmed via M0-M2
applies to both READ and WRITE bursts; when M9 = 1, the
programmed burst length applies to READ bursts, but
write accesses are single-location (nonburst) accesses.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| IS42S32200B-6TLI | 512K Bits x 32 Bits x 4 Banks (64-MBIT) SYNCHRONOUS DYNAMIC RAM |
| IS42S32200B-7T | 512K Bits x 32 Bits x 4 Banks (64-MBIT) SYNCHRONOUS DYNAMIC RAM |
| IS42S32200B-7TI | 512K Bits x 32 Bits x 4 Banks (64-MBIT) SYNCHRONOUS DYNAMIC RAM |
| IS42S32200B-7TL | 512K Bits x 32 Bits x 4 Banks (64-MBIT) SYNCHRONOUS DYNAMIC RAM |
| IS42S32200B-7TLI | 512K Bits x 32 Bits x 4 Banks (64-MBIT) SYNCHRONOUS DYNAMIC RAM |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| IS42S32200B-6TLI | 制造商:Integrated Silicon Solution Inc 功能描述:DRAM Chip SDRAM 64M-Bit 2Mx32 3.3V 86-Pin TSOP-II |
| IS42S32200B-6TL-TR | 制造商:Integrated Silicon Solution Inc 功能描述:DRAM Chip SDRAM 64M-Bit 2Mx32 3.3V 86-Pin TSOP-II T/R |
| IS42S32200B-6T-TR | 制造商:Integrated Silicon Solution Inc 功能描述:DRAM Chip SDRAM 64M-Bit 2Mx32 3.3V 86-Pin TSOP-II T/R |
| IS42S32200B-7T | 制造商:Integrated Silicon Solution Inc 功能描述:DRAM Chip SDRAM 64M-Bit 2Mx32 3.3V 86-Pin TSOP-II 制造商:Integrated Silicon Solution Inc 功能描述:2M X 32 SYNCHRONOUS DRAM, 6.5 ns, PDSO86 |
| IS42S32200B-7TI | 制造商:Integrated Silicon Solution Inc 功能描述:DRAM Chip SDRAM 64M-Bit 2Mx32 3.3V 86-Pin TSOP-II |
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