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參數(shù)資料
| 型號(hào)： | IS42S32200B-6TI |
| 廠商： | INTEGRATED SILICON SOLUTION INC |
| 元件分類： | DRAM |
| 英文描述： | 512K Bits x 32 Bits x 4 Banks (64-MBIT) SYNCHRONOUS DYNAMIC RAM |
| 中文描述： | 2M X 32 SYNCHRONOUS DRAM, 5.5 ns, PDSO86 |
| 封裝： | 0.400 INCH, PLASTIC, TSOP2-86 |
| 文件頁數(shù)： | 30/56頁 |
| 文件大小： | 537K |
| 代理商： | IS42S32200B-6TI |
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IS42S32200B
ISSI
30
Integrated Silicon Solution, Inc. — www.issi.com —
1-800-379-4774
Rev. 00C
09/29/03
DON'T CARE
CLK
COMMAND
BANK n
BANK m
ADDRESS
DQ
T0
T1
T2
T3
T4
T5
T6
T7
NOP
NOP
NOP
NOP
NOP
NOP
D
IN
a
D
IN
a+1
D
OUT
b
D
OUT
b+1
BANK n,
COL a
BANK m,
COL b
CAS Latency - 3 (BANK m)
t
RP - BANK n
t
RP - BANK m
Precharge
BANK n
BANK m
Page Active
WRITE with Burst of 4
Interrupt Burst, Write-Back
t
WR
- BANK n
Precharge
Page Active
READ with Burst of 4
Internal States
DON'T CARE
CLK
COMMAND
BANK n
BANK m
ADDRESS
DQ
T0
T1
T2
T3
T4
T5
T6
T7
NOP
NOP
NOP
NOP
NOP
NOP
BANK n,
COL a
BANK m,
COL b
t
RP - BANK n
RP - BANK m
Write-Back
WRITE - AP
BANK n
WRITE - AP
BANK m
Page Active
WRITE with Burst of 4
Interrupt Burst, Write-Back
t
WR
- BANK n
Precharge
Page Active
WRITE with Burst of 4
Internal States
D
IN
a
D
IN
a+1
D
IN
a+2
D
IN
b
D
IN
b+1
D
IN
b+2
D
IN
b+3
WRITE with Auto Precharge
3. Interrupted by a READ (with or without auto precharge):
A READ to bank m will interrupt a WRITE on bank n when
registered, with the data-out appearing
CAS latency
later.
The PRECHARGE to bank n will begin after t
WR
is met,
where t
WR
begins when the READ to bank m is registered.
The last valid
WRITE
to bank n will be data-in registered
one clock prior to the READ to bank m.
4. Interrupted by a WRITE (with or without auto precharge):
A
WRITE
to bank m will interrupt a
WRITE
on bank n when
registered. The PRECHARGE to bank n will begin after
t
WR
is met, where t
WR
begins when the WRITE to bank
m is registered. The last valid data WRITE to bank n will
be data registered one clock prior to a WRITE to bank m.
Fig CAP 3 - WRITE With Auto Precharge interrupted by a READ
Fig CAP 4 - WRITE With Auto Precharge interrupted by a WRITE
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| IS42S32200B-6TL | 512K Bits x 32 Bits x 4 Banks (64-MBIT) SYNCHRONOUS DYNAMIC RAM |
| IS42S32200B-6TLI | 512K Bits x 32 Bits x 4 Banks (64-MBIT) SYNCHRONOUS DYNAMIC RAM |
| IS42S32200B-7T | 512K Bits x 32 Bits x 4 Banks (64-MBIT) SYNCHRONOUS DYNAMIC RAM |
| IS42S32200B-7TI | 512K Bits x 32 Bits x 4 Banks (64-MBIT) SYNCHRONOUS DYNAMIC RAM |
| IS42S32200B-7TL | 512K Bits x 32 Bits x 4 Banks (64-MBIT) SYNCHRONOUS DYNAMIC RAM |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| IS42S32200B-6TL | 制造商:Integrated Silicon Solution Inc 功能描述:DRAM Chip SDRAM 64M-Bit 2Mx32 3.3V 86-Pin TSOP-II |
| IS42S32200B-6TLI | 制造商:Integrated Silicon Solution Inc 功能描述:DRAM Chip SDRAM 64M-Bit 2Mx32 3.3V 86-Pin TSOP-II |
| IS42S32200B-6TL-TR | 制造商:Integrated Silicon Solution Inc 功能描述:DRAM Chip SDRAM 64M-Bit 2Mx32 3.3V 86-Pin TSOP-II T/R |
| IS42S32200B-6T-TR | 制造商:Integrated Silicon Solution Inc 功能描述:DRAM Chip SDRAM 64M-Bit 2Mx32 3.3V 86-Pin TSOP-II T/R |
| IS42S32200B-7T | 制造商:Integrated Silicon Solution Inc 功能描述:DRAM Chip SDRAM 64M-Bit 2Mx32 3.3V 86-Pin TSOP-II 制造商:Integrated Silicon Solution Inc 功能描述:2M X 32 SYNCHRONOUS DRAM, 6.5 ns, PDSO86 |
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