參數(shù)資料
型號(hào): IS42S16400D
廠商: Integrated Silicon Solution, Inc.
英文描述: 1 Meg Bits x 16 Bits x 4 Banks (64-MBIT) SYNCHRONOUS DYNAMIC RAM
中文描述: 1梅格位× 16位× 4銀行(64兆位)同步動(dòng)態(tài)RAM
文件頁(yè)數(shù): 14/57頁(yè)
文件大?。?/td> 578K
代理商: IS42S16400D
IS42S16400D
ISSI
14
Integrated Silicon Solution, Inc. — www.issi.com —
1-800-379-4774
Rev. C
07/05/06
AC ELECTRICAL CHARACTERISTICS
(1,2,3)
-6
-7
Symbol
Parameter
Min.
Max.
Min.
Max.
Units
t
CK3
t
CK2
Clock Cycle Time
CAS
Latency = 3
CAS
Latency = 2
6
7
ns
ns
7.5
7.5
t
AC3
t
AC2
Access Time From CLK
(4,6)
CAS
Latency = 3
CAS
Latency = 2
5
6
5.4
6
ns
ns
t
CHI
CLK HIGH Level Width
2
2.5
ns
t
CL
CLK LOW Level Width
2
2.5
ns
t
OH3
t
OH2
Output Data Hold Time
(6)
CAS
Latency = 3
CAS
Latency = 2
2.5
2.5
2.7
3
ns
ns
t
LZ
Output LOW Impedance Time
0
0
ns
t
HZ3
t
HZ2
Output HIGH Impedance Time
(5)
CAS
Latency = 3
CAS
Latency = 2
5
6
5.4
6
ns
ns
t
DS
Input Data Setup Time
1.5
1.5
ns
t
DH
Input Data Hold Time
0.8
0.8
ns
t
AS
Address Setup Time
1.5
1.5
ns
t
AH
Address Hold Time
0.8
0.8
ns
t
CKS
CKE Setup Time
1.5
1.5
ns
t
CKH
CKE Hold Time
0.8
0.8
ns
t
CKA
CKE to CLK Recovery Delay Time
1CLK+3
1CLK+3
ns
t
CS
Command Setup Time (
CS
,
RAS
,
CAS
,
WE
, DQM)
1.5
2.0
ns
t
CH
Command Hold Time (
CS
,
RAS
,
CAS
,
WE
, DQM)
0.8
1
ns
t
RC
Command Period (REF to REF / ACT to ACT)
60
63
ns
t
RAS
Command Period (ACT to PRE)
42
100,000
42
100,000
ns
t
RP
Command Period (PRE to ACT)
18
20
ns
t
RCD
Active Command To Read / Write Command Delay Time
18
20
ns
t
RRD
Command Period (ACT [0] to ACT[1])
12
14
ns
t
DPL
or
t
WR
Input Data To Precharge
Command Delay time
CAS
Latency = 3
2CLK
2CLK
ns
CAS
Latency = 2
2CLK
2CLK
ns
t
DAL
Input Data To Active / Refresh
Command Delay time (During Auto-Precharge)
CAS
Latency = 3
2CLK+t
RP
2CLK+t
RP
ns
CAS
Latency = 2
2CLK+t
RP
2CLK+t
RP
ns
t
T
Transition Time
1
10
1
10
ns
t
REF
Notes:
1. When power is first applied, memory operation should be started 200 μs after V
DD
and V
DDQ
reach their stipulated voltages.
Also note that the power-on sequence must be executed before starting memory operation.
2. Measured with t
T
= 1 ns.
3. The reference level is 1.4 V when measuring input signal timing. Rise and fall times are measured between V
IH
(min.) and V
IL
(max.).
4. Access time is measured at 1.4V with the load shown in the figure below.
5. The time t
HZ
(max.) is defined as the time required for the output voltage to transition by ± 200 mV from V
OH
(min.) or V
OL
(max.)
when the output is in the high impedance state.
6. If clock rising time is longer than 1ns, tr/
2
- 0.5ns should be added to the parameter.
Refresh Cycle Time (4096)
64
64
ms
相關(guān)PDF資料
PDF描述
IS42S16400D-6T 1 Meg Bits x 16 Bits x 4 Banks (64-MBIT) SYNCHRONOUS DYNAMIC RAM
IS42S16400D-6TL 1 Meg Bits x 16 Bits x 4 Banks (64-MBIT) SYNCHRONOUS DYNAMIC RAM
IS42S16400D-6TLI 1 Meg Bits x 16 Bits x 4 Banks (64-MBIT) SYNCHRONOUS DYNAMIC RAM
IS42S16400D-7BL 1 Meg Bits x 16 Bits x 4 Banks (64-MBIT) SYNCHRONOUS DYNAMIC RAM
IS42S16400D-7BLI 1 Meg Bits x 16 Bits x 4 Banks (64-MBIT) SYNCHRONOUS DYNAMIC RAM
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