- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄377550 > IS42S16400-6T (INTEGRATED SILICON SOLUTION INC) 1 Meg Bits x 16 Bits x 4 Banks (64-MBIT) SYNCHRONOUS DYNAMIC RAM PDF資料下載
參數(shù)資料
| 型號： | IS42S16400-6T |
| 廠商： | INTEGRATED SILICON SOLUTION INC |
| 元件分類： | DRAM |
| 英文描述： | 1 Meg Bits x 16 Bits x 4 Banks (64-MBIT) SYNCHRONOUS DYNAMIC RAM |
| 中文描述： | 4M X 16 SYNCHRONOUS DRAM, 5.5 ns, PDSO54 |
| 封裝： | 0.400 INCH, TSOP2-54 |
| 文件頁數(shù)： | 10/54頁 |
| 文件大?。?/td> | 580K |
| 代理商： | IS42S16400-6T |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁當(dāng)前第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁
IS42S16400
ISSI
10
Integrated Silicon Solution, Inc.
—
1-800-379-4774
TARGET SPECIFICATION
Rev. C
05/04/01
7. READs or WRITEs to bank m listed in the Command (Action) column include READs or WRITEs with auto precharge enabled
and READs or WRITEs with auto precharge disabled.
8. CONCURRENT AUTO PRECHARGE: Bank n will initiate the AUTO PRECHARGE command when its burst has been inter-
rupted by bank m
’
s burst.
9. Burst in bank n continues as initiated.
10. For a READ without auto precharge interrupted by a READ (with or without auto precharge), the READ to bank m will interrupt the
READ on bank n, CAS latency later (Consecutive READ Bursts).
11. For a READ without auto precharge interrupted by a WRITE (with or without auto precharge), the WRITE to bank m will interrupt
the READ on bank n when registered (READ to WRITE). DQM should be used one clock prior to the WRITE command to prevent
bus contention.
12. For a WRITE without auto precharge interrupted by a READ (with or without auto precharge), the READ to bank m will interrupt
the WRITE on bank n when registered (WRITE to READ), with the data-out appearing CAS latency later. The last valid WRITE to
bank n will be data-in registered one clock prior to the READ to bank m.
13. For a WRITE without auto precharge interrupted by a WRITE (with or without auto precharge), the WRITE to bank m will interrupt
the WRITE on bank n when registered (WRITE to WRITE). The last valid WRITE to bank n will be data-in registered one clock
prior to the READ to bank m.
14. For a READ with auto precharge interrupted by a READ (with or without auto precharge), the READ to bank m will interrupt the
READ on bank n, CAS latency later. The PRECHARGE to bank n will begin when the READ to bank m is registered (Fig CAP 1).
15. For a READ with auto precharge interrupted by a WRITE (with or without auto precharge), the WRITE to bank m will interrupt the
READ on bank n when registered. DQM should be used two clocks prior to the WRITE command to prevent bus contention. The
PRECHARGE to bank n will begin when the WRITE to bank m is registered (Fig CAP 2).
16. For a WRITE with auto precharge interrupted by a READ (with or without auto precharge), the READ to bank m will interrupt the
WRITE on bank n when registered, with the data-out appearing CAS latency later. The PRECHARGE to bank n will begin after
t
WR
is met, where t
WR
begins when the READ to bank m is registered. The last valid WRITE to bank n will be data-in registered
one clock prior to the READ to bank m (Fig CAP 3).
17. For a WRITE with auto precharge interrupted by a WRITE (with or without auto precharge), the WRITE to bank m will interrupt the
WRITE on bank n when registered. The PRECHARGE to bank n will begin after t
WR
is met, where t WR begins when the WRITE
to bank m is registered. The last valid WRITE to bank n will be data registered one clock prior to the WRITE to bank m (Fig CAP 4).
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| IS42S16400-7T | 1 Meg Bits x 16 Bits x 4 Banks (64-MBIT) SYNCHRONOUS DYNAMIC RAM |
| IS42S16400-7TI | 1 Meg Bits x 16 Bits x 4 Banks (64-MBIT) SYNCHRONOUS DYNAMIC RAM |
| IS42S16800A1 | 8Meg x16 128-MBIT SYNCHRONOUS DRAM |
| IS42S16800A1-7TL | 8Meg x16 128-MBIT SYNCHRONOUS DRAM |
| IS42S16800B-7TL | 16Meg x 8, 8Meg x16 128-MBIT SYNCHRONOUS DRAM |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| IS42S16400-7T | 制造商:ISSI 制造商全稱:Integrated Silicon Solution, Inc 功能描述:1 Meg Bits x 16 Bits x 4 Banks (64-MBIT) SYNCHRONOUS DYNAMIC RAM |
| IS42S16400-7TI | 制造商:Integrated Silicon Solution Inc 功能描述: |
| IS42S16400A | 制造商:ISSI 制造商全稱:Integrated Silicon Solution, Inc 功能描述:1 Meg Bits x 16 Bits x 4 Banks (64-MBIT) SYNCHRONOUS DYNAMIC RAM |
| IS42S16400A-7T | 制造商:Integrated Silicon Solution Inc 功能描述:DRAM Chip SDRAM 64M-Bit 4Mx16 3.3V 54-Pin TSOP-II 制造商:Integrated Silicon Solution Inc 功能描述:SDRAM, 4M x 16, 54 Pin, Plastic, TSOP |
| IS42S16400A-7TI | 制造商:Integrated Silicon Solution Inc 功能描述:DRAM Chip SDRAM 64M-Bit 4Mx16 3.3V 54-Pin TSOP-II |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。